Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

icebreaker/fomu: Fix SPRAM split.

This commit is contained in:
Florent Kermarrec 2021-09-30 09:32:26 +02:00
parent 5addd7f7d8
commit 82653cf66f
3 changed files with 21 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
litex_boards/targets/1bitsquared_icebreaker.py
View File

@ -92,10 +92,15 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0*kB,
size = 64*kB,
linker = True)
)
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["sram"].origin + 64*kB,
origin = self.bus.regions["psram"].origin + 64*kB,
size = 64*kB,
linker = True)
)

9
litex_boards/targets/1bitsquared_icebreaker_bitsy.py
View File

@ -87,10 +87,15 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0*kB,
size = 64*kB,
linker = True)
)
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["sram"].origin + 64*kB,
origin = self.bus.regions["psram"].origin + 64*kB,
size = 64*kB,
linker = True)
)

9
litex_boards/targets/kosagi_fomu.py
View File

@ -97,10 +97,15 @@ class BaseSoC(SoCCore):
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0*kB,
size = 64*kB,
linker = True)
)
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["sram"].origin + 64*kB,
origin = self.bus.regions["psram"].origin + 64*kB,
size = 64*kB,
linker = True)
)