[enh] taking advantage of pins directly connected
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2023 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Colorlight 5A-75B PCB and IOs have been documented by @miek and @smunaut:
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# https://github.com/q3k/chubby75/tree/master/5a-75b
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# The Colorlight 5A-907 PCB, which is heavily based on the 5A-75B has been documented by @chmouss:
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# https://github.com/chmousset/colorlight_reverse
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeECP5Platform
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@ -13,7 +17,7 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io_v7_0 = [ # Documented by @miek
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_io_v7_0 = [ # Documented by @miek and @chmouss
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# Clk
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("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
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@ -25,8 +29,14 @@ _io_v7_0 = [ # Documented by @miek
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("P11")), # led (J19 DATA_LED-)
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Subsignal("rx", Pins("M13")), # btn (J19 KEY+)
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Subsignal("tx", Pins("P15")), # FAN pin 1
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Subsignal("rx", Pins("L14")), # FAN pin 2
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IOStandard("LVCMOS33")
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),
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("uartbone", 0,
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Subsignal("tx", Pins("F15")), # EXT_VOL pin 1
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Subsignal("rx", Pins("E16")), # EXT_VOL pin 2
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IOStandard("LVCMOS33")
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),
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@ -95,20 +105,29 @@ _io_v7_0 = [ # Documented by @miek
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),
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# USB
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# To use the USB:
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# shunt R124 and R134
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# remove R107
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# connect on R107's pad towards FPGA to R124 shunt through a 1.5k resistor
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("usb", 0,
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Subsignal("d_p", Pins("M8")),
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Subsignal("d_n", Pins("R2")),
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Subsignal("pullup", Pins("P4")),
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Subsignal("d_p", Pins("F15")), # EXT_VOL pin 1
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Subsignal("d_n", Pins("E16")), # EXT_VOL pin 2
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Subsignal("pullup", Pins("A12")), # R107's pad towards FPGA
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IOStandard("LVCMOS33")
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),
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]
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# From https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.0.md
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# Documented by @chmouss
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_connectors_v7_0 = [
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("j1", "- "),
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("j2", "- "),
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("j3", "- "),
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("j4", "- "),
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("door", "- - P16"),
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("smoke", "- - M14 -"),
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("fan", "- P15 L14"),
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("ext_vol", "- F15 E16"),
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# pinout: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
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("j1", "- L2 K1 F12 J14 B16 - J5 K2 F3 F1 T4 G3 - G2 H3 R5 H5 J4 K3 - R8 G1 K4 C2 P8 E3"),
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("j2", "- L2 K1 F12 J14 B16 - J2 J1 H4 K5 R7 P1 - R1 L5 P7 F2 P4 R2 - N7 M8 M9 T6 M7 R6"),
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("j3", "- L2 K1 F12 J14 B16 - G4 G5 M11 N11 L13 P12 - K15 N12 G13 L16 K16 J15 - G12 J16 J12 H15 F13 G16"),
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("j4", "- L2 K1 F12 J14 B16 - F5 F4 H13 J13 E15 H12 - G14 H14 D16 G15 A15 F16 - F14 A14 E13 B14 E14 A13"),
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]
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@ -138,6 +138,8 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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with_rst = kwargs["uart_name"] not in ["serial", "crossover"] # serial_rx shared with user_btn_n.
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if board == "i5a-907":
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with_rst = True
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with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
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self.crg = _CRG(platform, sys_clk_freq,
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use_internal_osc = use_internal_osc,
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@ -178,17 +180,19 @@ class BaseSoC(SoCCore):
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# Leds -------------------------------------------------------------------------------------
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# Disable leds when serial is used.
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if platform.lookup_request("serial", loose=True) is None and with_led_chaser:
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if platform.lookup_request("serial", loose=True) is None and with_led_chaser or board == "i5a-907":
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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self.add_uartbone(name="uartbone")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=colorlight_5a_75b.Platform, description="LiteX SoC on Colorlight 5A-75X.")
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parser.add_target_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).")
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parser.add_target_argument("--board", default="5a-75b", help="Board type (5a-75b, 5a-75e or i5a-907).")
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parser.add_target_argument("--revision", default="7.0", help="Board revision (6.0, 6.1, 7.0 or 8.0).")
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parser.add_target_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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