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targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR

This commit is contained in:
Gwenhael Goavec-Merou 2024-07-22 15:18:27 +02:00
parent ab732011b3
commit 938bf8b3a6
4 changed files with 4 additions and 4 deletions
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2
litex_boards/targets/lattice_certuspro_nx_evn.py
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@ -39,7 +39,7 @@ class _CRG(LiteXModule):
self.rst_n = platform.request("user_btn", 0)
# Clocking
self.hf_clk = NXOSCA()
self.hf_clk = NXOSCA(platform)
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)

2
litex_boards/targets/lattice_certuspro_nx_vvml.py
View File

@ -39,7 +39,7 @@ class _CRG(LiteXModule):
self.rst_n = platform.request("gsrn")
# Built in OSC
self.hf_clk = NXOSCA()
self.hf_clk = NXOSCA(platform)
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)

2
litex_boards/targets/lattice_crosslink_nx_evn.py
View File

@ -34,7 +34,7 @@ class _CRG(LiteXModule):
self.cd_sys = ClockDomain()
# Built in OSC
self.hf_clk = NXOSCA()
self.hf_clk = NXOSCA(platform)
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)

2
litex_boards/targets/lattice_crosslink_nx_vip.py
View File

@ -38,7 +38,7 @@ class _CRG(LiteXModule):
# TODO: replace with PLL
# Clocking
self.sys_clk = sys_osc = NXOSCA()
self.sys_clk = sys_osc = NXOSCA(platform)
sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
rst_n = platform.request("gsrn")