trenz_tec0117: Use new integrated reset from GW1NPLL.

2021-07-14 09:55:00 +02:00 · 2021-07-14 09:55:00 +02:00 · 94b985ac56
parent 6e31d12fa9
commit 94b985ac56
1 changed files with 0 additions and 1 deletions
--- a/litex_boards/targets/trenz_tec0117.py
+++ b/litex_boards/targets/trenz_tec0117.py
@ -47,7 +47,6 @@ class _CRG(Module):
        self.comb += pll.reset.eq(~rst_n)
        pll.register_clkin(clk100, 100e6)
        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        self.comb += self.cd_sys.rst.eq(~rst_n) # FIXME: Move to GW1NPLL and use lock.

 # BaseSoC ------------------------------------------------------------------------------------------