sitlinv_stlv7325_v2: Add default value to vccio.

2023-06-07 15:00:49 +02:00 · 2023-06-07 15:00:49 +02:00 · 96175a9986
parent d874d344d2
commit 96175a9986
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/platforms/sitlinv_stlv7325_v2.py
+++ b/litex_boards/platforms/sitlinv_stlv7325_v2.py
@ -486,7 +486,7 @@ class Platform(Xilinx7SeriesPlatform):
    default_clk_name   = "clk200"
    default_clk_period = 1e9/200e6

-    def __init__(self, vccio):
+    def __init__(self, vccio="3.3V"):
        assert vccio in ["2.5V", "3.3V"]
        Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _get_io(vccio), _connectors, toolchain="vivado")
        self.add_platform_command("""