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colorlight_5a_75x: Disable full_memory_we for l2 cache by default 

Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70.
With full_mem_we:
```
Info: 	              DP16KD:    41/   56    73%
```
Without:
```
Info: 	              DP16KD:    29/   56    51%
```
This commit is contained in:
David Sawatzke 2021-08-08 14:37:46 +02:00
parent 4d20cfe5cd
commit 9f5e8d4864
1 changed files with 5 additions and 3 deletions
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8
litex_boards/targets/colorlight_5a_75x.py
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@ -152,9 +152,11 @@ class BaseSoC(SoCCore):
else: else:
sdram_cls = M12L16161A sdram_cls = M12L16161A
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate), module = sdram_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192) l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_full_memory_we = False,
) )
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------