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Merge pull request #279 from mmicko/efinix_t20_flash 

Enable writing to flash for T20
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enjoy-digital 2021-10-15 18:38:08 +02:00 committed by GitHub
parent 3730d96709 1f65d37121
commit a4d330dd2c
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1 changed files with 6 additions and 0 deletions
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6
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
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@ -86,6 +86,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit") parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
builder_args(parser) builder_args(parser)
@ -103,5 +104,10 @@ def main():
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, f"outflow/{soc.build_name}.bit")) prog.load_bitstream(os.path.join(builder.gateware_dir, f"outflow/{soc.build_name}.bit"))
if args.flash:
from litex.build.openfpgaloader import OpenFPGALoader
prog = OpenFPGALoader("trion_t120_bga576")
prog.flash(0, os.path.join(builder.gateware_dir, f"outflow/{soc.build_name}.hex"))
if __name__ == "__main__": if __name__ == "__main__":
main() main()