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Merge branch 'master' of https://github.com/litex-hub/litex-boards

This commit is contained in:
Lukas F. Hartmann 2023-04-25 20:29:11 +02:00
parent d160a5ad5d a0594a0708
commit a9e3e3c050
3 changed files with 3 additions and 1 deletions
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2
litex_boards/platforms/terasic_de10nano.py
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@ -67,7 +67,7 @@ _io = [
# HDMI # HDMI
("hdmi", 0, ("hdmi", 0,
Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), Subsignal("tx_d_r", Pins("AD12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")), Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")),
Subsignal("tx_clk", Pins("AG5")), Subsignal("tx_clk", Pins("AG5")),

1
litex_boards/targets/xilinx_alveo_u200.py
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@ -75,6 +75,7 @@ class BaseSoC(SoCCore):
self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
cmd_latency = 1,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
is_rdimm = True) is_rdimm = True)
self.add_sdram("sdram", self.add_sdram("sdram",

1
litex_boards/targets/xilinx_alveo_u250.py
View File

@ -74,6 +74,7 @@ class BaseSoC(SoCCore):
self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
cmd_latency = 1,
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
is_rdimm = True) is_rdimm = True)
self.add_sdram("sdram", self.add_sdram("sdram",