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use the right DRAM chip for the QMTech Altera boards

This commit is contained in:
Hans Baier 2021-11-06 08:45:03 +07:00
parent ee5638a96b
commit b2813cfb70
3 changed files with 6 additions and 6 deletions
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4
litex_boards/targets/qmtech_10cl006.py
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@ -21,7 +21,7 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litedram.modules import IS42S16160 from litedram.modules import W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.video import VideoVGAPHY
@ -99,7 +99,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(sys_clk_freq, sdram_rate), module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192) l2_cache_size = kwargs.get("l2_size", 8192)
) )

4
litex_boards/targets/qmtech_5cefa2.py
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@ -22,7 +22,7 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litedram.modules import IS42S16160 from litedram.modules import W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.video import VideoVGAPHY
@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(sys_clk_freq, sdram_rate), module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192) l2_cache_size = kwargs.get("l2_size", 8192)
) )

4
litex_boards/targets/qmtech_ep4ce15.py
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@ -21,7 +21,7 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litedram.modules import IS42S16160 from litedram.modules import W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.video import VideoVGAPHY
@ -97,7 +97,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(sys_clk_freq, sdram_rate), module = W9825G6KH6(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192) l2_cache_size = kwargs.get("l2_size", 8192)
) )