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terasic_sockit: Review/Cleanup for consistency with other boards.
This commit is contained in:
Florent Kermarrec
parent
53a767c85c
commit
b54eed0859
2 changed files with 39 additions and 48 deletions
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@ -12,16 +12,16 @@ from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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# Clk.
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("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
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# Leds
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# Leds.
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("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")),
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# Buttons
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# Buttons.
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("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")),
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("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")),
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("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")),
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@ -33,7 +33,7 @@ _io = [
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("user_sw", 2, Pins("AC28"), IOStandard("3.3-V LVTTL")),
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("user_sw", 3, Pins("AC29"), IOStandard("3.3-V LVTTL")),
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# MiSTer SDRAM via GPIO expansion board J2
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# MiSTer SDRAM (via GPIO expansion board on J2).
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("sdram_clock", 0, Pins("D10"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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@ -41,8 +41,7 @@ _io = [
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"D12 A11 B6 D11 A10")),
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Subsignal("ba", Pins("B5 A4")),
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Subsignal("cs_n", Pins("A3")),
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# CKE not connected on XS 2.2/2.4
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Subsignal("cke", Pins("B3")),
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Subsignal("cke", Pins("B3")), # CKE not connected on XS 2.2/2.4.
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Subsignal("ras_n", Pins("E9")),
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Subsignal("cas_n", Pins("A6")),
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Subsignal("we_n", Pins("A5")),
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@ -50,13 +49,12 @@ _io = [
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"F14 G15 F15 H15 G13 A13 H14 B13",
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"C13 C8 B12 B8 F13 C12 B11 E13"),
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),
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# DQML/DQMH not connected on XS 2.2/2.4
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Subsignal("dm", Pins("AB27 AA26")),
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Subsignal("dm", Pins("AB27 AA26")), # DQML/DQMH not connected on XS 2.2/2.4
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IOStandard("3.3-V LVTTL"),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
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),
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# DDR3 SDRAM
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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"AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13",
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@ -108,7 +106,7 @@ _io = [
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Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")
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),
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# VGA
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# VGA.
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("vga", 0,
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Subsignal("sync_n", Pins("AG2")),
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Subsignal("blank_n", Pins("AH3")),
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@ -121,13 +119,13 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# IrDA
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# IrDA.
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("irda", 0,
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Subsignal("irda_rxd", Pins("AH2")),
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IOStandard("3.3-V LVTTL")
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),
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# Temperatue
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# Temperatue.
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("temperature", 0,
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Subsignal("temp_cs_n", Pins("AF8")),
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Subsignal("temp_din", Pins("AG7")),
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@ -136,7 +134,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# Audio
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# Audio.
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("audio", 0,
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Subsignal("aud_adclrck", Pins("AG30")),
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Subsignal("aud_adcdat", Pins("AC27")),
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@ -150,6 +148,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# GPIO Serial.
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("gpio_serial", 0,
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Subsignal("tx", Pins("J3:9")),
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Subsignal("rx", Pins("J3:10")),
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@ -157,24 +156,22 @@ _io = [
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]
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# Connectors ---------------------------------------------------------------------------------------
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# Since the numbering of the connectors in the documentation is 1-based
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# I added a dummy pin (-) to the beginning to each connector
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# to make the numbering in the code consistent with the documentation
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_connectors_hsmc_gpio_daughterboard = [
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("J2", "- G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " +
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"C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " +
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"A6 E9 A3 B5 A4 B6 B1 C2 B2 D2"),
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("J2p", "- D1 E1 E11 F11"), # top to bottom, starting with 57
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("J2p", "- D1 E1 E11 F11"), # Top to bottom, starting with 57.
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("J3", "- AB27 F8 AA26 F9 B3 G8 C3 H8 D4 H7 - - " +
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"E4 J7 E2 K8 E3 K7 E6 J9 E7 J10 C4 J12 D5 G10 C5 J12 - - " +
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"D6 K12 F6 G11 G7 G12 D7 A8 E8 A9"),
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("J3p", "- C9 C10 H12 H13"), # top to bottom, starting with 117
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("J3p", "- C9 C10 H12 H13"), # Top to bottom, starting with 117.
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("J4", "- - - AD3 AE1 AD4 AE2 - - AB3 AC1 - - " +
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"AB4 AC2 - - Y3 AA1 Y4 AA2 - - V3 W1 V4 W2 - - - -" +
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"T3 U1 T4 R1 - R2 P3 U2 P4 -"),
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("J4p", "- M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # top to bottom, starting with 169
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("J4p", "- M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # Top to bottom, starting with 169.
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]
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# Platform -----------------------------------------------------------------------------------------
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@ -4,36 +4,29 @@
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#
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# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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"""
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This class provides basic support for the Arrow SoCKit.
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Since the SoCKit has its USB2UART attached to the HPS
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system, it is not available to the FPGA and thus the only
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way to communicate is via JTAG serial which is configured
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by default.
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To access it, you can use the nios2_terminal application
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included in the Intel/Altera quartus distribution.
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"""
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import os
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import argparse
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from migen.fhdl.module import Module
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from migen.fhdl.structure import Signal, ClockDomain, ClockSignal
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.builder import Builder, builder_args, builder_argdict
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from litex.soc.integration.soc_core import SoCCore, soc_core_argdict, soc_core_args
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoVGAPHY
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from litex.build.io import DDROutput
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from migen import *
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from litex_boards.platforms import terasic_sockit
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from litedram.modules import _TechnologyTimings, _SpeedgradeTimings, SDRModule, AS4C32M16
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from litedram.phy import HalfRateGENSDRPHY, GENSDRPHY
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoVGAPHY
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from litex.build.io import DDROutput
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from litedram.modules import AS4C32M16
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from litedram.phy import HalfRateGENSDRPHY, GENSDRPHY
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# DRAM Module for XS board v2.2 ----------------------------------------------------------------------
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# FIXME: Move to litedram.modules.
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from litedram.modules import _TechnologyTimings, _SpeedgradeTimings, SDRModule
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class W9825G6KH6(SDRModule):
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"""
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Winbond W9825G6KH-6 chip on Mister SDRAM XS board v2.2
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@ -77,8 +70,8 @@ class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2"):
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self.sdram_rate = sdram_rate
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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if with_sdram:
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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@ -126,11 +119,7 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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if mister_sdram == "xs_v22":
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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@ -165,6 +154,11 @@ class BaseSoC(SoCCore):
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self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga")
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self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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