gadgetfactory_papilio_pro: Cosmetic cleanups.

This commit is contained in:
Florent Kermarrec 2023-01-17 15:43:12 +01:00
parent ec4d203eb6
commit b9874685a5
2 changed files with 74 additions and 41 deletions

View File

@ -1,18 +1,29 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2023 Fabien Caura <fabien@acathla.tk>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxSpartan6Platform
from litex.build.xilinx.programmer import XC3SProg
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
# Clk / Rst.
("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
# Leds.
("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
# Serial.
("serial", 1,
Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("P38")),
Subsignal("clk", Pins("P70")),
@ -27,22 +38,30 @@ _io = [
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
# SDR SDRAM.
("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("sdram", 0,
Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44",
"P43 P41 P40 P141 P35 P34")),
Subsignal("a", Pins(
"P140 P139 P138 P137 P46 P45 P44",
"P43 P41 P40 P141 P35 P34"
)),
Subsignal("ba", Pins("P143 P142")),
Subsignal("cs_n", Pins("P1")),
Subsignal("cke", Pins("P33")),
Subsignal("ras_n", Pins("P2")),
Subsignal("cas_n", Pins("P5")),
Subsignal("we_n", Pins("P6")),
Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")),
Subsignal("dq", Pins(
"P9 P10 P11 P12 P14 P15 P16 P8",
"P21 P22 P23 P24 P26 P27 P29 P30"
)),
Subsignal("dm", Pins("P7 P17")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
)
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"),
@ -55,7 +74,7 @@ _connectors = [
# Arcade MegaWing V1.3 pinout
_arcade_megawing = [
# VGA
# VGA.
("vga", 0,
Subsignal("r", Pins("C:4 C:5 C:6 C:7")),
Subsignal("g", Pins("B:4 B:5 B:6 B:7")),
@ -64,7 +83,8 @@ _arcade_megawing = [
Subsignal("hsync_n", Pins("C:3")),
IOStandard("LVCMOS33")
),
# Buttons
# Buttons.
("buttons", 0,
Subsignal("up", Pins("C:8")),
Subsignal("down", Pins("C:10")),
@ -72,7 +92,8 @@ _arcade_megawing = [
Subsignal("right", Pins("C:13")),
IOStandard("LVCMOS33")
),
# Joysticks ports
# Joysticks ports.
("joy", 0,
Subsignal("up", Pins("C:8")),
Subsignal("down", Pins("C:10")),
@ -91,7 +112,8 @@ _arcade_megawing = [
Subsignal("fire2", Pins("A:3")),
IOStandard("LVCMOS33")
),
# ps2 port
# PS2 ports.
("ps2", 0,
Subsignal("clk", Pins("C:1")),
Subsignal("data", Pins("C:0")),
@ -102,22 +124,29 @@ _arcade_megawing = [
Subsignal("data", Pins("A:12")),
IOStandard("LVCMOS33")
),
# LEDs
# Leds.
("amw_user_led", 0, Pins("A:7"), IOStandard("LVCMOS33")),
("amw_user_led", 1, Pins("A:6"), IOStandard("LVCMOS33")),
("amw_user_led", 2, Pins("A:5"), IOStandard("LVCMOS33")),
("amw_user_led", 3, Pins("A:4"), IOStandard("LVCMOS33")),
# Reset button
# Reset button.
("reset_button", 0, Pins("P85"), IOStandard("LVCMOS33") )
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxSpartan6Platform):
default_clk_name = "clk32"
default_clk_period = 31.25
default_clk_period = 1e9/32e6
def __init__(self, toolchain="ise"):
XilinxSpartan6Platform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")
def do_finalize(self, fragment):
XilinxSpartan6Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6)

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@ -25,6 +25,8 @@ from litex.soc.cores.led import LedChaser
from litedram.modules import MT48LC4M16
from litedram.phy import s6ddrphy, GENSDRPHY, HalfRateGENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
self.rst = Signal()
@ -58,7 +60,7 @@ class _CRG(LiteXModule):
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
### BaseSoC
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=80e6,
@ -85,23 +87,24 @@ class BaseSoC(SoCCore):
l2_cache_size = 0
)
# LEDs -------------------------------------------------------------------------------------
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Video Terminal
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
self.platform.add_extension(gadgetfactory_papilio_pro._arcade_megawing)
self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform(),
description="LiteX SoC on Papilio Pro")
parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform, description="LiteX SoC on Papilio Pro.")
parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
args = parser.parse_args()
@ -110,6 +113,7 @@ def main():
with_video_terminal = args.with_video_terminal,
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)