Merge pull request #471 from Acathla-fr/papilio
Target/Platform Papilio Pro added (with Arcade MegaWing)
This commit is contained in:
enjoy-digital
GitHub
commit
ec4d203eb6
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxSpartan6Platform
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from litex.build.xilinx.programmer import XC3SProg
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_io = [
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("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
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("serial", 1,
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Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("mosi", Pins("P64")),
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Subsignal("miso", Pins("P65"), Misc("PULLUP")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("dq", Pins("P64", "P65")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44",
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"P43 P41 P40 P141 P35 P34")),
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Subsignal("ba", Pins("P143 P142")),
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Subsignal("cs_n", Pins("P1")),
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Subsignal("cke", Pins("P33")),
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Subsignal("ras_n", Pins("P2")),
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Subsignal("cas_n", Pins("P5")),
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Subsignal("we_n", Pins("P6")),
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Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")),
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Subsignal("dm", Pins("P7 P17")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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)
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]
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_connectors = [
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# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"),
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("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"),
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("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134")
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# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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]
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# Extensions --------------------------------------------------------------------------------------
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# Arcade MegaWing V1.3 pinout
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_arcade_megawing = [
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# VGA
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("vga", 0,
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Subsignal("r", Pins("C:4 C:5 C:6 C:7")),
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Subsignal("g", Pins("B:4 B:5 B:6 B:7")),
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Subsignal("b", Pins("B:0 B:1 B:2 B:3")),
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Subsignal("vsync_n", Pins("C:2")),
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Subsignal("hsync_n", Pins("C:3")),
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IOStandard("LVCMOS33")
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),
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# Buttons
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("buttons", 0,
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Subsignal("up", Pins("C:8")),
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Subsignal("down", Pins("C:10")),
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Subsignal("left", Pins("C:11")),
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Subsignal("right", Pins("C:13")),
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IOStandard("LVCMOS33")
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),
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# Joysticks ports
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("joy", 0,
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Subsignal("up", Pins("C:8")),
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Subsignal("down", Pins("C:10")),
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Subsignal("left", Pins("C:11")),
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Subsignal("right", Pins("C:13")),
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Subsignal("fire1", Pins("C:9")),
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Subsignal("fire2", Pins("C:15")),
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IOStandard("LVCMOS33")
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),
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("joy", 1,
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Subsignal("up", Pins("B:12")),
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Subsignal("down", Pins("B:14")),
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Subsignal("left", Pins("B:15")),
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Subsignal("right", Pins("A:1")),
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Subsignal("fire1", Pins("B:13")),
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Subsignal("fire2", Pins("A:3")),
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IOStandard("LVCMOS33")
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),
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# ps2 port
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("ps2", 0,
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Subsignal("clk", Pins("C:1")),
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Subsignal("data", Pins("C:0")),
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IOStandard("LVCMOS33")
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),
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("ps2", 1,
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Subsignal("clk", Pins("A:13")),
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Subsignal("data", Pins("A:12")),
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IOStandard("LVCMOS33")
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),
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# LEDs
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("amw_user_led", 0, Pins("A:7"), IOStandard("LVCMOS33")),
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("amw_user_led", 1, Pins("A:6"), IOStandard("LVCMOS33")),
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("amw_user_led", 2, Pins("A:5"), IOStandard("LVCMOS33")),
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("amw_user_led", 3, Pins("A:4"), IOStandard("LVCMOS33")),
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# Reset button
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("reset_button", 0, Pins("P85"), IOStandard("LVCMOS33") )
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]
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class Platform(XilinxSpartan6Platform):
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default_clk_name = "clk32"
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default_clk_period = 31.25
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def __init__(self, toolchain="ise"):
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XilinxSpartan6Platform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Fabien Caura <fabien@acathla.tk>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from litex.gen import LiteXModule
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from litex.build.io import DDROutput
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from litex_boards.platforms import gadgetfactory_papilio_pro
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC4M16
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from litedram.phy import s6ddrphy, GENSDRPHY, HalfRateGENSDRPHY
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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self.cd_vga = ClockDomain()
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# # #
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# Clk / Rst
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clk32 = platform.request("clk32")
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# PLL
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self.pll = pll = S6PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk32, 32e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_vga, 40e6)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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### BaseSoC
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=80e6,
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with_led_chaser=True,
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with_video_terminal = False,
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**kwargs):
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platform = gadgetfactory_papilio_pro.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
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kwargs["cpu_variant"] = "minimal"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Papilio Pro", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC4M16(sys_clk_freq, "1:2"),
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l2_cache_size = 0
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)
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# LEDs -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Video Terminal
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if with_video_terminal:
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self.platform.add_extension(gadgetfactory_papilio_pro._arcade_megawing)
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self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform(),
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description="LiteX SoC on Papilio Pro")
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parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_video_terminal = args.with_video_terminal,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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