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vc707: fix default clock frequency

This commit is contained in:
Michael Betz 2021-02-19 22:47:18 -08:00
parent 7442c2dada
commit c32e790421
1 changed files with 1 additions and 1 deletions
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2
litex_boards/platforms/vc707.py
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@ -629,7 +629,7 @@ _connectors = [
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk156" default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6 default_clk_period = 1e9/156.25e6
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")