vc707: fix default clock frequency
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7442c2dada
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c32e790421
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@ -629,7 +629,7 @@ _connectors = [
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class Platform(XilinxPlatform):
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default_clk_name = "clk156"
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default_clk_period = 1e9/156.5e6
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default_clk_period = 1e9/156.25e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")
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