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Default to 60 Mhz system clock on ECP5 Evaluation Board 

Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
This commit is contained in:
DurandA 2019-08-09 11:57:39 +02:00
parent 9e6dccc277
commit c90950e319
1 changed files with 2 additions and 2 deletions
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4
litex_boards/community/targets/ecp5_evn.py
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@ -62,8 +62,8 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis') help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
parser.add_argument("--sys-clk-freq", default=50e6, parser.add_argument("--sys-clk-freq", default=60e6,
help="system clock frequency (default=50MHz)") help="system clock frequency (default=60MHz)")
parser.add_argument("--x5-clk-freq", type=int, parser.add_argument("--x5-clk-freq", type=int,
help="use X5 oscillator as system clock at the specified frequency") help="use X5 oscillator as system clock at the specified frequency")
args = parser.parse_args() args = parser.parse_args()