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LiteX boards files
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DurandA c90950e319 Default to 60 Mhz system clock on ECP5 Evaluation Board 
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
 		2019-08-09 11:58:30 +02:00
litex_boards Default to 60 Mhz system clock on ECP5 Evaluation Board 2019-08-09 11:58:30 +02:00
test test_targets: add trellisboard 2019-07-12 19:26:31 +02:00
.gitignore gitignore: ignore temporary python files 2019-06-19 12:51:06 -07:00
.travis.yml add travis-ci 2019-06-24 12:41:33 +02:00
README init repo with litex official boards 2019-06-10 17:11:36 +02:00
setup.py Turn litex_boards.partner into module 2019-07-01 19:36:34 +02:00

README 

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          / /  (_) /____ | |/_/___/ _ )___  ___ ________/ /__
         / /__/ / __/ -_)>  </___/ _  / _ \/ _ `/ __/ _  (_-<
        /____/_/\__/\__/_/|_|   /____/\___/\_,_/_/  \_,_/___/

                       LiteX boards files

              Copyright 2012-2019 / LiteX-Hub community

[> Intro
--------
Supported boards files (platforms/targets) for LiteX.

Official:
---------
Platforms / Targets actively tested and included in the CI system.

Partner:
-------
Platforms / Targets supported by other groups/partners.

Community:
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Platforms / Targets supported by the community in a "best effort" manner.