DurandA c90950e319 Default to 60 Mhz system clock on ECP5 Evaluation Board ... Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.		2019-08-09 11:58:30 +02:00
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community	Default to 60 Mhz system clock on ECP5 Evaluation Board	2019-08-09 11:58:30 +02:00
official	Merge branch 'master' of http://github.com/litex-hub/litex-boards	2019-07-12 19:19:31 +02:00
partner	partner/targets/trellisboard: cleanup/update	2019-07-12 19:39:12 +02:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00