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litex-boards
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snickerdoodle: Rename to krtkl_snicker_doodle and do minor cosmetic changes.

This commit is contained in:
Florent Kermarrec 2022-01-03 17:09:17 +01:00
parent b48d96c40d
commit dc61d383e6
3 changed files with 18 additions and 21 deletions
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1
litex_boards/__init__.py
View File

@ -18,6 +18,7 @@ vendors = [
"fairwaves",
"hackaday",
"kosagi",
"krtkl",
"lattice",
"lambdaconcept",
"linsn",

14
litex_boards/platforms/snickerdoodle.py → litex_boards/platforms/krtkl_snickerdoodle.py
View File

@ -1,8 +1,8 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>,
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
@ -11,13 +11,13 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst - A placeholder for an external clock
# Clk / Rst - FIXME: A placeholder for an external clock
("clk100", 0, Pins("H16"), IOStandard("LVCMOS33")),
# Leds - A placeholder for an external LED
# Leds - FIXME: A placeholder for an external LED
("user_led", 0, Pins("G14"), IOStandard("LVCMOS33")),
# UART - A placeholder for an external UART
# UART - FIXME: A placeholder for an external UART
("serial", 0,
Subsignal("tx", Pins("D19")),
Subsignal("rx", Pins("D20")),
@ -73,11 +73,13 @@ class Platform(XilinxPlatform):
def __init__(self):
XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado")
self.default_clk_period = 1e9 / self.default_clk_freq
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128a")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
self.default_clk_period)
self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)

24
litex_boards/targets/snickerdoodle.py → litex_boards/targets/krtkl_snickerdoodle.py
View File

@ -3,8 +3,8 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>,
# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
import os
@ -63,12 +63,10 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self,
sys_clk_freq = int(100e6),
ext_clk_freq = None,
with_led_chaser = True,
xci_file = None,
**kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True,
ext_clk_freq = None,
xci_file = None,
**kwargs):
platform = snickerdoodle.Platform()
@ -77,11 +75,9 @@ class BaseSoC(SoCCore):
platform.default_clk_period = 1e9 / ext_clk_freq
if kwargs.get("cpu_type", None) == "zynq7000":
kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
self.mem_map = {
'csr': 0x4000_0000, # Zynq GP0 default
}
kwargs["integrated_sram_size"] = 0
kwargs["with_uart"] = False
self.mem_map = {"csr": 0x4000_0000} # Zynq GP0 default
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
@ -108,8 +104,6 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
platform.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(