targets/de10nano: fix typo.
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@ -76,6 +76,7 @@ class BaseSoC(SoCCore):
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# SDR SDRAM --------------------------------------------------------------------------------
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# SDR SDRAM --------------------------------------------------------------------------------
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if with_mister_sdram and not self.integrated_main_ram_size:
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if with_mister_sdram and not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.sdrphy,
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phy = self.sdrphy,
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module = AS4C32M16(sys_clk_freq, sdram_rate),
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module = AS4C32M16(sys_clk_freq, sdram_rate),
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