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quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3.

This commit is contained in:
Florent Kermarrec 2021-11-14 09:26:29 +01:00
parent 2d3422869c
commit ed67b91fcc
1 changed files with 7 additions and 10 deletions
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17
litex_boards/targets/quicklogic_quickfeather.py
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@ -23,18 +23,19 @@ from litex.soc.cores.gpio import *
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, is_eoss3_cpu=False): def __init__(self, platform, with_eos_s3=False):
self.rst = Signal() self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
# # # # # #
class Open(Signal): pass if with_eos_s3:
# Use clocks generated by the EOS-S3 CPU.
if is_eoss3_cpu:
self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0")) self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst) self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
else: else:
# Use clocks generated by the qlal4s3b_cell_macro.
class Open(Signal): pass
self.specials += Instance("qlal4s3b_cell_macro", self.specials += Instance("qlal4s3b_cell_macro",
o_Sys_Clk0 = self.cd_sys.clk, o_Sys_Clk0 = self.cd_sys.clk,
o_Sys_Clk0_Rst = self.cd_sys.rst, o_Sys_Clk0_Rst = self.cd_sys.rst,
@ -49,11 +50,7 @@ class BaseSoC(SoCCore):
platform = quicklogic_quickfeather.Platform() platform = quicklogic_quickfeather.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "eos-s3": kwargs["cpu_type"] = kwargs.get("cpu_type", None)
is_eoss3_cpu = True
else:
is_eoss3_cpu = False
kwargs["cpu_type"] = None
kwargs["with_uart"] = False kwargs["with_uart"] = False
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QuickLogic QuickFeather", ident = "LiteX SoC on QuickLogic QuickFeather",
@ -61,7 +58,7 @@ class BaseSoC(SoCCore):
**kwargs) **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, is_eoss3_cpu) self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos-s3")
# GPIOIn -> interrupt test # GPIOIn -> interrupt test
if with_gpioin: if with_gpioin: