quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3.
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@ -23,18 +23,19 @@ from litex.soc.cores.gpio import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, is_eoss3_cpu=False):
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def __init__(self, platform, with_eos_s3=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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class Open(Signal): pass
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if is_eoss3_cpu:
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if with_eos_s3:
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# Use clocks generated by the EOS-S3 CPU.
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self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
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self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
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else:
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# Use clocks generated by the qlal4s3b_cell_macro.
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class Open(Signal): pass
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self.specials += Instance("qlal4s3b_cell_macro",
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o_Sys_Clk0 = self.cd_sys.clk,
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o_Sys_Clk0_Rst = self.cd_sys.rst,
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@ -49,11 +50,7 @@ class BaseSoC(SoCCore):
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platform = quicklogic_quickfeather.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "eos-s3":
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is_eoss3_cpu = True
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else:
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is_eoss3_cpu = False
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kwargs["cpu_type"] = None
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kwargs["cpu_type"] = kwargs.get("cpu_type", None)
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kwargs["with_uart"] = False
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QuickLogic QuickFeather",
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@ -61,7 +58,7 @@ class BaseSoC(SoCCore):
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, is_eoss3_cpu)
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self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos-s3")
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# GPIOIn -> interrupt test
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if with_gpioin:
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