Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #297 from sergachev/master 

Fix Sipeed Tang Nano 4k example compilation; adapt Gowin PLL class changes
This commit is contained in:
enjoy-digital 2021-12-02 09:14:32 +01:00 committed by GitHub
parent b3175e4a9c 666ef9dad3
commit efa1f46356
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex_boards/targets/sipeed_tang_nano.py
View File

@ -57,7 +57,7 @@ class _CRG(Module):
rst_n = platform.request("user_btn", 0) rst_n = platform.request("user_btn", 0)
# PLL. # PLL.
self.submodules.pll = pll = GW1NPLL(device="GW1N-1") self.submodules.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~rst_n) self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk24, 24e6) pll.register_clkin(clk24, 24e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)

9
litex_boards/targets/sipeed_tang_nano_4k.py
View File

@ -12,7 +12,7 @@ import argparse
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock.gowin_gw1nsr import GW1NSRPLL from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
@ -40,7 +40,7 @@ class _CRG(Module):
rst_n = platform.request("user_btn", 0) rst_n = platform.request("user_btn", 0)
# PLL # PLL
self.submodules.pll = pll = GW1NSRPLL(device="GW1NSR-4C") self.submodules.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~rst_n) self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk27, 27e6) pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
@ -48,7 +48,7 @@ class _CRG(Module):
# Video PLL # Video PLL
if with_video_pll: if with_video_pll:
self.submodules.video_pll = video_pll = GW1NSRPLL(device="GW1NSR-4C") self.submodules.video_pll = video_pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
self.comb += video_pll.reset.eq(~rst_n) self.comb += video_pll.reset.eq(~rst_n)
video_pll.register_clkin(clk27, 27e6) video_pll.register_clkin(clk27, 27e6)
self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi = ClockDomain()
@ -72,6 +72,9 @@ class BaseSoC(SoCCore):
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0 kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0
kwargs["cpu_type"] = 'vexriscv'
kwargs["cpu_variant"] = 'minimal'
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Tang Nano 4K", ident = "LiteX SoC on Tang Nano 4K",