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Support HPC Store XC7K420T board

This commit is contained in:
Hans Baier 2022-05-11 10:20:49 +07:00
parent d1096a2cd0
commit f383ad3938
2 changed files with 216 additions and 202 deletions
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64
litex_boards/platforms/hpcstore_xc7k420t.py
View File

@ -13,9 +13,11 @@ from litex.build.openocd import OpenOCD
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
def _get_io(io_standard):
_io = [ _io = [
# Clk / Rst # Clk / Rst
("clk100", 0, Pins("U24"), IOStandard("LVCMOS33")), ("clk100", 0, Pins("U24"), io_standard),
("diffclk100", 0, ("diffclk100", 0,
Subsignal("p", Pins("U22"), IOStandard("LVDS_25")), Subsignal("p", Pins("U22"), IOStandard("LVDS_25")),
Subsignal("n", Pins("U23"), IOStandard("LVDS_25")) Subsignal("n", Pins("U23"), IOStandard("LVDS_25"))
@ -33,7 +35,7 @@ _io = [
# Buttons # Buttons
("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")), ("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")),
("user_btn_n", 1, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V ("cpu_reset_n", 0, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V
# I2C / AT24C04 # I2C / AT24C04
("i2c", 0, ("i2c", 0,
@ -67,7 +69,7 @@ _io = [
"G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23 " + \ "G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23 " + \
"N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19 " + \ "N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19 " + \
"K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28 "), "K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28 "),
IOStandard("SSTL15_T_DCI")), IOStandard("SSTL15")),
Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"), Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"),
IOStandard("DIFF_SSTL15")), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"),
@ -78,7 +80,6 @@ _io = [
Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), Subsignal("odt", Pins("J28"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
Misc("VCCAUX_IO=NORMAL")
), ),
# DDR3 SDRAM near power supply # DDR3 SDRAM near power supply
@ -99,7 +100,7 @@ _io = [
"AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27 " + \ "AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27 " + \
"AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16 " + \ "AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16 " + \
"AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14 "), "AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14 "),
IOStandard("SSTL15_T_DCI")), IOStandard("SSTL15")),
Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"), Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"),
IOStandard("DIFF_SSTL15")), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"), Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"),
@ -107,10 +108,9 @@ _io = [
Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")), Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")), Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")), Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AH24"), IOStandard("SSTL15")), Subsignal("odt", Pins("AG20"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")), Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
Misc("VCCAUX_IO=NORMAL")
), ),
# Sata # Sata
@ -131,7 +131,7 @@ _io = [
# PCIe # PCIe
("pcie_x1", 0, ("pcie_x1", 0,
Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), Subsignal("rst_n", Pins("W21"), io_standard),
Subsignal("clk_p", Pins("T6")), Subsignal("clk_p", Pins("T6")),
Subsignal("clk_n", Pins("T5")), Subsignal("clk_n", Pins("T5")),
Subsignal("rx_p", Pins("P6")), Subsignal("rx_p", Pins("P6")),
@ -140,7 +140,7 @@ _io = [
Subsignal("tx_n", Pins("N3")) Subsignal("tx_n", Pins("N3"))
), ),
("pcie_x2", 0, ("pcie_x2", 0,
Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), Subsignal("rst_n", Pins("W21"), io_standard),
Subsignal("clk_p", Pins("T6")), Subsignal("clk_p", Pins("T6")),
Subsignal("clk_n", Pins("T5")), Subsignal("clk_n", Pins("T5")),
Subsignal("rx_p", Pins("")), Subsignal("rx_p", Pins("")),
@ -150,7 +150,7 @@ _io = [
Subsignal("tx_n", Pins("N3 P1")) Subsignal("tx_n", Pins("N3 P1"))
), ),
("pcie_x4", 0, ("pcie_x4", 0,
Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), Subsignal("rst_n", Pins("W21"), io_standard),
Subsignal("clk_p", Pins("T6")), Subsignal("clk_p", Pins("T6")),
Subsignal("clk_n", Pins("T5")), Subsignal("clk_n", Pins("T5")),
Subsignal("rx_p", Pins("P6 R4 U4 V6")), Subsignal("rx_p", Pins("P6 R4 U4 V6")),
@ -159,7 +159,7 @@ _io = [
Subsignal("tx_n", Pins("N3 P1 T1 V1")) Subsignal("tx_n", Pins("N3 P1 T1 V1"))
), ),
("pcie_x8", 0, ("pcie_x8", 0,
Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS33")), Subsignal("rst_n", Pins("W21"), io_standard),
Subsignal("clk_p", Pins("T6")), Subsignal("clk_p", Pins("T6")),
Subsignal("clk_n", Pins("T5")), Subsignal("clk_n", Pins("T5")),
Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")), Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")),
@ -169,41 +169,47 @@ _io = [
), ),
# SFP # SFP A
("sfp_a", 0, # SFP A ("sfp_a", 0,
Subsignal("txp", Pins("A8")), Subsignal("txp", Pins("A8")),
Subsignal("txn", Pins("A7")), Subsignal("txn", Pins("A7")),
Subsignal("rxp", Pins("D10")), Subsignal("rxp", Pins("D10")),
Subsignal("rxn", Pins("D9")), Subsignal("rxn", Pins("D9")),
Subsignal("sda", Pins("C15")), Subsignal("sda", Pins("C15"), io_standard),
Subsignal("scl", Pins("A15")), Subsignal("scl", Pins("A15"), io_standard),
), ),
("sfp_a_tx", 0, # SFP A ("sfp_a_tx", 0,
Subsignal("p", Pins("A8")), Subsignal("p", Pins("A8")),
Subsignal("n", Pins("A7")) Subsignal("n", Pins("A7"))
), ),
("sfp_a_rx", 0, # SFP A ("sfp_a_rx", 0,
Subsignal("p", Pins("D10")), Subsignal("p", Pins("D10")),
Subsignal("n", Pins("D9")) Subsignal("n", Pins("D9"))
), ),
("sfp_b", 0, # SFP B ("sfp_a_tx_disable_n", 0, Pins("Y20"), io_standard),
# SFP B
("sfp_b", 0,
Subsignal("txp", Pins("C8")), Subsignal("txp", Pins("C8")),
Subsignal("txn", Pins("C7")), Subsignal("txn", Pins("C7")),
Subsignal("rxp", Pins("F10")), Subsignal("rxp", Pins("F10")),
Subsignal("rxn", Pins("F9")), Subsignal("rxn", Pins("F9")),
Subsignal("sda", Pins("C14")), Subsignal("sda", Pins("C14"), io_standard),
Subsignal("scl", Pins("B14")), Subsignal("scl", Pins("B14"), io_standard),
), ),
("sfp_b_tx", 0, # SFP B ("sfp_b_tx", 0,
Subsignal("p", Pins("C8")), Subsignal("p", Pins("C8")),
Subsignal("n", Pins("C7")) Subsignal("n", Pins("C7"))
), ),
("sfp_b_rx", 0, # SFP B ("sfp_b_rx", 0,
Subsignal("p", Pins("F10")), Subsignal("p", Pins("F10")),
Subsignal("n", Pins("F9")) Subsignal("n", Pins("F9"))
), ),
("sfp_b_tx_disable_n", 0, Pins("D14"), io_standard),
] ]
return _io
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
# #
@ -311,13 +317,15 @@ class Platform(XilinxPlatform):
default_clk_name = "diffclk100" default_clk_name = "diffclk100"
default_clk_period = 1e9/100e6 default_clk_period = 1e9/100e6
def __init__(self): def __init__(self, io_voltage="3.3V"):
XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ISE") assert io_voltage in ["2.5V", "3.3V"], "io_voltage must be '2.5V' or '3.3V' acording to the board jumper"
self.add_platform_command(""" io_standard = IOStandard("LVCMOS33") if io_voltage == "3.3V" else IOStandard("LVCMOS25")
set_property CONFIG_VOLTAGE 3.3 [current_design] _io = _get_io(io_standard)
set_property CFGBVS VCCO [current_design]
""") XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ise")
self.toolchain.bitstream_commands = [ self.toolchain.bitstream_commands = [
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
"set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]", "set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]",

20
litex_boards/targets/hpcstore_xc7k420t.py
View File

@ -17,7 +17,7 @@ import os
from migen import * from migen import *
from litex_boards.platforms import aliexpress_stlv7325 from litex_boards.platforms import hpcstore_xc7k420t
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
@ -25,7 +25,7 @@ from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster from litex.soc.cores.bitbang import I2CMaster
from litedram.modules import MT8JTF12864 from litedram.modules import K4B1G0446F
from litedram.phy import s7ddrphy from litedram.phy import s7ddrphy
from litepcie.phy.s7pciephy import S7PCIEPHY from litepcie.phy.s7pciephy import S7PCIEPHY
@ -38,6 +38,7 @@ class _CRG(Module):
self.rst = Signal() self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain()
self.clock_domains.cd_sys4x_dqs = ClockDomain()
self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_idelay = ClockDomain()
# # # # # #
@ -47,11 +48,12 @@ class _CRG(Module):
rst_n = platform.request("cpu_reset_n") rst_n = platform.request("cpu_reset_n")
# PLL. # PLL.
self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.submodules.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(~rst_n | self.rst) self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk100, 100e6) pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
@ -61,11 +63,12 @@ class _CRG(Module):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), def __init__(self, sys_clk_freq=int(100e6),
io_voltage="3.3V",
with_led_chaser = True, with_led_chaser = True,
with_pcie = False, with_pcie = False,
with_sata = False, with_sata = False,
**kwargs): **kwargs):
platform = aliexpress_stlv7325.Platform() platform = hpcstore_xc7k420t.Platform(io_voltage)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -75,14 +78,16 @@ class BaseSoC(SoCCore):
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), # we need to use A7DDRPHY instead of K7DDRPHY, because the 420T has no ODELAYE2
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram", 0),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6
) )
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"), module = K4B1G0446F(sys_clk_freq, "1:4", "800"),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),
) )
@ -134,7 +139,7 @@ def main():
target_group.add_argument("--build", action="store_true", help="Build design.") target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group() target_group.add_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.") target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.") target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.") target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.")
@ -144,6 +149,7 @@ def main():
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
io_voltage = args.io_voltage,
with_pcie = args.with_pcie, with_pcie = args.with_pcie,
with_sata = args.with_sata, with_sata = args.with_sata,
**soc_core_argdict(args) **soc_core_argdict(args)