Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

targets/pcie: update LitePCIe constraints.

Browse source
This commit is contained in:
Florent Kermarrec 2020-05-07 12:15:52 +02:00
parent d34c3baf15
commit f9939532b6
4 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
litex_boards/targets/acorn_cle_215.py
View file

@ -118,6 +118,7 @@ class PCIeSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 64, data_width = 64,
bar0_size = 0x20000) bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")
self.comb += platform.request("pcie_clkreq_n").eq(0) self.comb += platform.request("pcie_clkreq_n").eq(0)

1
litex_boards/targets/aller.py
View file

@ -119,6 +119,7 @@ class PCIeSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 64, data_width = 64,
bar0_size = 0x20000) bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")

1
litex_boards/targets/nereid.py
View file

@ -117,6 +117,7 @@ class PCIeSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 64, data_width = 64,
bar0_size = 0x20000) bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")

1
litex_boards/targets/tagus.py
View file

@ -117,6 +117,7 @@ class PCIeSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 64, data_width = 64,
bar0_size = 0x20000) bar0_size = 0x20000)
self.pcie_phy.add_timing_constraints(platform)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy") self.add_csr("pcie_phy")