litex-boards

Commit Graph

Author	SHA1	Message	Date
Florent Kermarrec	00ff61baa9	targets: Simplify clock domains and remove useless reset_less. rst was not directly assigned/used on reset_less clock domains, so reset_less property was not really useful. With the changes on stream.CDC, having a rst (Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this also fixes targets.	2022-04-01 11:30:38 +02:00
Florent Kermarrec	9d452b0d74	targets: Create target_group for target arguments.	2022-03-21 18:37:40 +01:00
Florent Kermarrec	cc8da9d341	targets: Simplify imports and switch to LiteXSocArgumentParser. CPU parameters are now selectively exposed to the user: ./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters. ./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.	2022-03-21 16:59:40 +01:00
Florent Kermarrec	773444a7dd	targets: Switch to get_bios_filename/get_bitstream_filename.	2022-03-17 09:21:05 +01:00
Florent Kermarrec	fccb952c4b	target: Remove ident_version=True no longer required.	2022-01-18 17:13:02 +01:00
Florent Kermarrec	53dc00eab7	targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description. Also do minor adjustments while doing this.	2022-01-05 17:06:40 +01:00
alainlou	1b676f929a	cleanup and ease of use - update README - delete some unnecessary toolchain commands (copied from trenz boards) - use minimal cpu_variant by default when vexriscv is selected	2021-10-03 13:21:45 -04:00
alainlou	1333f89ed6	rz_easyfpga: adjust SDRAM clk phase - also add 1:2 rate	2021-09-22 00:26:28 -04:00
Alain Lou	610e82d774	Add initial RZ-EasyFPGA support! (#270 )	2021-09-21 09:55:22 +02:00

9 Commits