Florent Kermarrec
|
8113b491db
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aller/nereid/tagus: update litepcie
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2020-01-21 21:26:23 +01:00 |
|
Florent Kermarrec
|
f9619c4a8f
|
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
|
2020-01-16 10:51:35 +01:00 |
|
Florent Kermarrec
|
028d4a78aa
|
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
|
2020-01-13 15:20:37 +01:00 |
|
Florent Kermarrec
|
48476be9e2
|
aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address
|
2019-12-14 22:10:04 +01:00 |
|
Florent Kermarrec
|
7184032555
|
aller/neired/tagus: fix gateware/software build directory
|
2019-12-14 11:29:15 +01:00 |
Derek Kozel
|
4334ba9527
|
partner/aller, nereid, tagus: Remove deprecated param
get_csr_header parameter with_shadow_base
removed/deprecated in litex 2a8d8c8f. New default
behavior matches the desired behavior in these targets.
|
2019-12-14 01:04:28 +00:00 |
|
Derek Kozel
|
3012cf75fe
|
partner/aller, nereid, tagus: Use updated csr APIs
litex commit 8be5824e258b84df240d34636aaa539124b92c65 simplified the handling
of csr regions and constants.
|
2019-12-14 01:00:52 +00:00 |
|
Florent Kermarrec
|
5193f7155a
|
partner/aller,nereid & tagus: fix compilation
|
2019-12-03 09:37:18 +01:00 |
|
Florent Kermarrec
|
f7fbfb4639
|
partner/community/targets: uniformize, improve presentation
|
2019-12-03 09:33:08 +01:00 |
|
Florent Kermarrec
|
c6bb34d78a
|
partner/targets/nereid: MT8KTF51264 now in LiteDRAM
|
2019-09-09 08:50:06 +02:00 |
|
Florent Kermarrec
|
ec5540454b
|
partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic
|
2019-09-02 11:43:30 +02:00 |
Rohit Singh
|
346621b9fc
|
partner: add platforms and targets for aller, tagus and nereid boards
|
2019-09-01 03:02:04 -05:00 |