45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
877bc4b45e
targets: Use full imports (vendor_board).
2022-05-02 12:55:11 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
f986855926
Merge pull request #372 from mkj/butterstick-ethdelay
...
butterstick: set ethernet rx_delay to 0ns
2022-04-21 09:00:13 +02:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
2a206def0f
targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less).
2022-03-22 17:32:35 +01:00
53c221a1fa
butterstick: set ethernet rx_delay to 0ns
...
The Microchip KSZ9031RNX PHY on the Butterstick has a default 1.2ns
internal RX delay so we shouldn't add the default 2ns MAC delay.
In testing with Linux on vexriscv I haven't seen any difference either
way, but with liteeth in Microwatt I have seen 30%+ packet loss when
receiving from certain ethernet devices (RTL8153 and AX88179 usb-gige
adapters, a GS105 switch didn't show the problem). Setting RX delay=0
resolves the problem. A TX delay is still required by the PHY.
2022-03-22 13:51:03 +08:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
5f2ccb2d32
targets: Switch from bridge to crossover.
2022-01-19 17:03:17 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
a4130556ac
gsd_butterstick: Add optional SYZYGY GPIO (--with-syzygy-gpio) to expose the 32 GPIOs on SYZYGY breakout board.
2022-01-06 18:37:42 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
fd2ec534a7
butterstick: Add extra pins
2021-12-05 20:33:28 +10:30
c8a8e943b5
butterstick: add --sdram-device option
...
Set 64M16 as default sdram-device.
Related to #298
2021-12-04 17:07:06 +10:30
91818bc5f0
targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments).
2021-10-26 17:01:55 +02:00
9e18d9bc34
gsd_butterstick: Remove ECLKBRIDGECS (not required).
2021-10-07 14:09:22 +02:00
68fb163a27
targets: Remove spiflash mapping on targets where it's no longer useful.
2021-09-14 18:35:13 +02:00
aa2209729f
gsd_butterstick: Force uart_name to crossover when set to serial.
2021-09-02 15:23:05 +02:00
fddca1cd40
gsd_butterstick: Add SDCard (SPI & SD modes) support.
2021-09-02 14:06:09 +02:00
596f430326
gsd_butterstick: Add SPI Flash support.
2021-09-02 11:28:21 +02:00
55ea71bd01
gsd_butterstick: Add initial DDR3 support.
...
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-01 19:21:16 +02:00
1f25a98476
butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone).
2021-09-01 18:03:13 +02:00
1f149ece6b
Add intial ButterStick support (with just Clk, Buttons and Leds).
2021-09-01 17:33:54 +02:00
Florent Kermarrec
Matt Johnston
Greg Davill