Florent Kermarrec
|
2b17dc1b89
|
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
|
2020-11-04 11:13:42 +01:00 |
|
Florent Kermarrec
|
c093d0d0fc
|
platforms: cleanup pass to uniformize comments/separators/orders.
|
2020-11-03 10:48:57 +01:00 |
|
Florent Kermarrec
|
814e7630e4
|
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
|
2020-10-13 12:10:29 +02:00 |
|
Florent Kermarrec
|
b9ac72cf78
|
targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
|
2020-09-01 13:38:32 +02:00 |
|
Florent Kermarrec
|
1781be166a
|
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
|
2020-08-23 15:00:17 +02:00 |
|
Florent Kermarrec
|
869ceadacb
|
targets: use platform.request_all on LedChaser.
|
2020-08-06 20:04:03 +02:00 |
|
Florent Kermarrec
|
7b1bf9d74a
|
targets: remove sdcard specific clock domain (now generated by the PHY).
|
2020-07-03 20:09:30 +02:00 |
|
Florent Kermarrec
|
31e6997e70
|
sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
|
2020-07-01 12:58:48 +02:00 |
|
Florent Kermarrec
|
7a48a61605
|
targets: add indentifier on all targets.
|
2020-06-30 18:11:04 +02:00 |
|
Florent Kermarrec
|
1356ebb416
|
targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
|
2020-06-29 16:42:53 +02:00 |
Owen Kirby
|
76a32ba8ec
|
Add Logicbone ECP5 board
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
|
2020-06-27 03:32:47 -07:00 |