Florent Kermarrec
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bd4e92ad13
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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Florent Kermarrec
|
2b17dc1b89
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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Florent Kermarrec
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c093d0d0fc
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platforms: cleanup pass to uniformize comments/separators/orders.
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2020-11-03 10:48:57 +01:00 |
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Florent Kermarrec
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814e7630e4
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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Florent Kermarrec
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b9ac72cf78
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targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
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2020-09-01 13:38:32 +02:00 |
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Florent Kermarrec
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1781be166a
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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Florent Kermarrec
|
869ceadacb
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targets: use platform.request_all on LedChaser.
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2020-08-06 20:04:03 +02:00 |
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Florent Kermarrec
|
7b1bf9d74a
|
targets: remove sdcard specific clock domain (now generated by the PHY).
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2020-07-03 20:09:30 +02:00 |
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Florent Kermarrec
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31e6997e70
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sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
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2020-07-01 12:58:48 +02:00 |
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Florent Kermarrec
|
7a48a61605
|
targets: add indentifier on all targets.
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2020-06-30 18:11:04 +02:00 |
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Florent Kermarrec
|
1356ebb416
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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2020-06-29 16:42:53 +02:00 |
Owen Kirby
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76a32ba8ec
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Add Logicbone ECP5 board
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
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2020-06-27 03:32:47 -07:00 |