Florent Kermarrec
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028d4a78aa
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targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
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2020-01-13 15:20:37 +01:00 |
|
Florent Kermarrec
|
30ea463b41
|
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
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2019-12-06 16:01:59 +01:00 |
|
Florent Kermarrec
|
f7fbfb4639
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partner/community/targets: uniformize, improve presentation
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2019-12-03 09:33:08 +01:00 |
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Florent Kermarrec
|
ac58d57a83
|
targets: import platforms from litex_boards.platforms
|
2019-08-26 09:09:40 +02:00 |
Arnaud Durand
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618f41bb1e
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Update ecp5_evn.py
The system clock was driven directly while it should be driven by the PLL.
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2019-08-22 02:27:50 +02:00 |
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DurandA
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c90950e319
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Default to 60 Mhz system clock on ECP5 Evaluation Board
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
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2019-08-09 11:58:30 +02:00 |
|
DurandA
|
4126ed21d5
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Add X5 clock and PLL to ECP5 Evaluation Board
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2019-08-09 11:54:38 +02:00 |
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DurandA
|
c7444fe19c
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Add ECP5 Evaluation Board
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2019-08-09 09:45:13 +02:00 |