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1021 Commits

Author SHA1 Message Date
Florent Kermarrec 5955a35372 Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). 2021-09-16 19:22:30 +02:00
Florent Kermarrec c0aed8a727 litex_m2_baseboard: Add Video Terminal support. 2021-09-16 18:54:50 +02:00
Florent Kermarrec 32a9256f3b litex_m2_baseboard: Add SDCard support. 2021-09-16 18:17:34 +02:00
Florent Kermarrec 0854a5d234 litex_m2_baseboard: Add Ethernet/Etherbone support. 2021-09-16 18:02:55 +02:00
Florent Kermarrec 8d2f75ca6d litex_m2_baseboard: Add PMODs connectors. 2021-09-16 17:48:53 +02:00
Florent Kermarrec 3ad0eb6992 Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons. 2021-09-16 17:44:50 +02:00
Tim Ansell 67756e53ae
Merge pull request #269 from kammoh/readme_zybo_fpga 
Update README.md
 2021-09-15 07:34:20 -07:00
Kamyar Mohajerani b75af2f21c
Update README.md 
FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
 2021-09-15 10:21:10 -04:00
Florent Kermarrec 078b1ed7b7 CONTRIBUTORS: Update. 2021-09-15 14:59:42 +02:00
enjoy-digital 26943959b5
Merge pull request #268 from trabucayre/runber_support 
Add runber support
 2021-09-15 08:32:05 +02:00
enjoy-digital 1ca77d6921
Merge pull request #267 from trabucayre/tangnano4k_fix_period 
platforms/sipeed_tang_nano_4k: fix period computation
 2021-09-15 08:28:19 +02:00
Gwenhael Goavec-Merou 7ccae3332d Add runber support 2021-09-15 06:50:57 +02:00
Gwenhael Goavec-Merou fed36afaba platforms/sipeed_tang_nano_4k: fix period computation 2021-09-15 06:46:29 +02:00
Florent Kermarrec 68fb163a27 targets: Remove spiflash mapping on targets where it's no longer useful. 2021-09-14 18:35:13 +02:00
Florent Kermarrec db91eda899 linsn_rv901t.py: Update Ethernet and add Etherbone support. 2021-09-13 19:35:05 +02:00
enjoy-digital b9f2a4c483
Merge pull request #266 from teknoman117/mojov3 
Add Mojo V3 support
 2021-09-10 14:01:59 +02:00
Nathaniel R. Lewis b8373a361d alchitry_mojo: new board 2021-09-10 02:40:31 -07:00
enjoy-digital d4613562a8
Merge pull request #265 from trabucayre/tangNano4K_connector 
platforms/sipeed_tang_nano_4k: add P6 and P7 connectors
 2021-09-09 11:43:05 +02:00
enjoy-digital cacb76450f
Merge pull request #264 from teknoman117/alchitry-au 
Add Alchitry Au as new board
 2021-09-09 11:42:37 +02:00
Florent Kermarrec 3622661fa8 test/test_targets: Remove build directory before build. 2021-09-09 11:36:18 +02:00
Gwenhael Goavec-Merou 945e48ea83 platforms/sipeed_tang_nano_4k: add P6 and P7 connectors 2021-09-09 11:35:14 +02:00
Florent Kermarrec 8d91489756 tang_nano_4k: Add more IOs. 2021-09-09 11:23:20 +02:00
Nathaniel R. Lewis 9bbdb87130 alchitry_au: new board 2021-09-09 00:03:19 -07:00
Florent Kermarrec 88534c6689 tang_nano_4k: Fix typo in sipeed. 2021-09-08 23:02:39 +02:00
Florent Kermarrec ce52c8c5ed beaglewire: Fix typo in qwertyembedded. 2021-09-08 21:29:29 +02:00
Florent Kermarrec ecebe7e267 Add initial SiSpeed Tang Nano 4K support (Led blink only for now...). 
./sispeed_tang_nano_4k.py --build --load

Build with Gowin EDA.
Load with OpenFPGALoader.
 2021-09-08 19:36:46 +02:00
Florent Kermarrec 129b95f9b5 sqrl_acorn: Update pre_placement_commands with new XilinxVivadCommands. 2021-09-08 16:27:30 +02:00
Florent Kermarrec 7fa22a494b arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2). 
On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
 2021-09-07 15:07:59 +02:00
Florent Kermarrec aa2209729f gsd_butterstick: Force uart_name to crossover when set to serial. 2021-09-02 15:23:05 +02:00
Florent Kermarrec fddca1cd40 gsd_butterstick: Add SDCard (SPI & SD modes) support. 2021-09-02 14:06:09 +02:00
Florent Kermarrec 596f430326 gsd_butterstick: Add SPI Flash support. 2021-09-02 11:28:21 +02:00
Florent Kermarrec 1bbbf5b3e7 gsd_butterstick: Add SYZYGY0/1 IOs to connectors. 2021-09-02 10:26:18 +02:00
Florent Kermarrec 55ea71bd01 gsd_butterstick: Add initial DDR3 support. 
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge


        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep  1 2021 19:09:52
 BIOS CRC passed (3d349845)

 Migen git sha1: 27dbf03
 LiteX git sha1: 315fbe18

--=============== SoC ==================--
CPU:		VexRiscv @ 75MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |01110000| delays: 02+-01
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: 02+-01
  m1, b00: |01110000| delays: 02+-01
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 15.6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-09-01 19:21:16 +02:00
Florent Kermarrec 1f25a98476 butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone). 2021-09-01 18:03:13 +02:00
Florent Kermarrec 1f149ece6b Add intial ButterStick support (with just Clk, Buttons and Leds). 2021-09-01 17:33:54 +02:00
enjoy-digital fb9bb17835
Merge pull request #259 from danc86/clnexevn-unreserve-spi-flash-pins 
lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
 2021-09-01 12:18:41 +02:00
Florent Kermarrec b3823d92b0 Add CONTRIBUTORS file. 2021-09-01 11:11:27 +02:00
Dan Callaghan 74c2178150 lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL 
Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved
for use by the sysCONFIG logic, and prevents user logic from assigning
them. This made it impossible to have a Litex design which accesses the
SPI flash on this board.

Remove the setting, so that we get the default behaviour which permits
user logic to assign these pins. In the unlikely event that someone
needs the pins to stay reserved for sysCONFIG after configuration (I'm
not sure why this would be needed) they could explicitly add this
command in their design.
 2021-09-01 18:47:17 +10:00
enjoy-digital 4731c500fb
Merge pull request #258 from danc86/clnexevn-device-arg 
lattice_crosslink_nx_evn: allow specifying the FPGA device
 2021-09-01 10:22:42 +02:00
Florent Kermarrec ce254208ff beaglewire: Review/Cleanup for consistency with other targets. 
- Now uses regular UART.
- Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build
- Can still be build with Crossover UART with --uart-name=crossover+bridge.
 2021-09-01 10:18:11 +02:00
Florent Kermarrec 35df77258a beaglewire: Rename to quertyembedded_beaglewire. 2021-09-01 09:36:09 +02:00
enjoy-digital 1e1f6a476d
Merge pull request #254 from ombhilare999/master 
beaglewire platform and target added
 2021-09-01 09:33:07 +02:00
Florent Kermarrec 4a18951651 tul_pynq_z2: Fix copyrights, remove PS7 part for now. 2021-09-01 08:50:56 +02:00
enjoy-digital 54c777a49c
Merge pull request #252 from developandplay/PYNQ-Z2 
WIP: Initial PYNQ Z2 support
 2021-09-01 08:46:44 +02:00
enjoy-digital 6a08a7973c
Merge pull request #251 from niw/fix_orangecrab_feather_spi_pad_name 
FIX: OrangeCrab Feather SPI pad name
 2021-08-31 18:59:09 +02:00
Florent Kermarrec 8f1c15bdb8 ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository). 2021-08-31 18:56:47 +02:00
Dhiru Kholia 781d83bab6 Add support for EBAZ4205 'Development' Board 
Usage:

```
./ebaz4205.py --cpu-type=vexriscv --build --load
```

```
$ pwd
litex-boards/litex_boards/targets
```

Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.

References:

- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example

Note: The `PS7` stuff remains untested via LiteX for now.
 2021-08-31 18:54:49 +02:00
Yoshimasa Niwa fc78c96444 FIX: OrangeCrab Feather SPI pad name 
**Problems**

`SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`.
However, `feather_spi` is using `sck` instead of `clk`, therefore
it is not able to use as-is for `SPIMaster`, for example,
with `add_spi` on Linux On LiteX VexRiscv.

**Solution**

In fact, `spisdcard` and other SPI related pad names are
using `clk`, only `feather_spi` is using `sck`.
Therefore, rename `sck` to `clk`.
 2021-08-29 17:59:45 -07:00
Florent Kermarrec b017a33f2b targets: Fix SPI Flash mapping on target supporting --with-spi-flash. 2021-08-23 18:05:40 +02:00
Dan Callaghan cc9e39286a lattice_crosslink_nx_evn: allow specifying the FPGA device 
This board is documented as having the LIFCL-40-9BG400C part, but some
versions of the board exist which were fitted with LIFCL-40-8BG400CES,
an engineering sample part. The distinction is important because the
engineering sample requires a different device ID to be embedded in the
bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load
it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red
"INITN" LED on this board).

Accept --device to allow the user to specify which FPGA part their board
has.
 2021-08-17 18:30:03 +10:00