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4 commits

Author SHA1 Message Date
Florent Kermarrec
6e31d12fa9 trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default). 2021-07-13 19:39:53 +02:00
Florent Kermarrec
2c5bf95f70 targets/trenz_tec0117: Switch to new GW1NPLL. 2021-04-30 11:32:24 +02:00
Florent Kermarrec
ba01776432 targets/add_sdram: Simplify call by removing useless arguments. 
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
 2021-03-29 15:28:31 +02:00
Florent Kermarrec
8a3cacae32 boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports). 2021-03-25 14:11:17 +01:00
Renamed from litex_boards/targets/tec0117.py (Browse further)