9 commits

Author	SHA1	Message	Date
DurandA	c90950e319	Default to 60 Mhz system clock on ECP5 Evaluation Board ... Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.	2019-08-09 11:58:30 +02:00
DurandA	9e6dccc277	Remove ECP5 Evaluation Board programmer	2019-08-09 11:54:49 +02:00
DurandA	4126ed21d5	Add X5 clock and PLL to ECP5 Evaluation Board	2019-08-09 11:54:38 +02:00
DurandA	c7444fe19c	Add ECP5 Evaluation Board	2019-08-09 09:45:13 +02:00
Florent Kermarrec	a88970a67f	move trellis board from community to partner	2019-07-12 19:23:21 +02:00
David Shah	a07e88d761	community: Add TrellisBoard ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-09 15:52:28 +01:00
Florent Kermarrec	aeddb93729	add copyright header to all files, udpate.	2019-06-24 12:13:54 +02:00
Florent Kermarrec	44d01edab9	dispatch platforms/targets by level of support	2019-06-10 18:59:49 +02:00
Florent Kermarrec	4213c75e48	init repo with litex official boards	2019-06-10 17:11:36 +02:00