DurandA
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c90950e319
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Default to 60 Mhz system clock on ECP5 Evaluation Board
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
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2019-08-09 11:58:30 +02:00 |
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DurandA
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4126ed21d5
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Add X5 clock and PLL to ECP5 Evaluation Board
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2019-08-09 11:54:38 +02:00 |
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DurandA
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c7444fe19c
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Add ECP5 Evaluation Board
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2019-08-09 09:45:13 +02:00 |
Florent Kermarrec
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a88970a67f
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move trellis board from community to partner
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2019-07-12 19:23:21 +02:00 |
David Shah
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a07e88d761
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community: Add TrellisBoard
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-09 15:52:28 +01:00 |
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Florent Kermarrec
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aeddb93729
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add copyright header to all files, udpate.
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2019-06-24 12:13:54 +02:00 |
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Florent Kermarrec
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44d01edab9
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dispatch platforms/targets by level of support
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2019-06-10 18:59:49 +02:00 |