DurandA c90950e319 Default to 60 Mhz system clock on ECP5 Evaluation Board ... Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.		2019-08-09 11:58:30 +02:00
..
ac701.py	add copyright header to all files, udpate.	2019-06-24 12:13:54 +02:00
de1soc.py	add copyright header to all files, udpate.	2019-06-24 12:13:54 +02:00
de2_115.py	add copyright header to all files, udpate.	2019-06-24 12:13:54 +02:00
de10lite.py	add copyright header to all files, udpate.	2019-06-24 12:13:54 +02:00
ecp5_evn.py	Default to 60 Mhz system clock on ECP5 Evaluation Board	2019-08-09 11:58:30 +02:00