Florent Kermarrec
|
cf9a9ff91b
|
de10nano: update copyrights, remove trailing whitespaces
|
2020-01-31 09:13:36 +01:00 |
Paul Sajna
|
36e1f1fe75
|
rename sw to user_sw
|
2020-01-30 05:01:46 -08:00 |
|
Paul Sajna
|
1631b071c3
|
finish up sdram, passes memtest
|
2020-01-30 03:41:44 -08:00 |
|
Paul Sajna
|
5091a1b40a
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WIP sdram module option
|
2020-01-29 13:59:57 -08:00 |
|
Paul Sajna
|
3a6a9258ce
|
add de10 nano board
add iostandard to hdmi
|
2020-01-29 00:21:51 -08:00 |
|
Florent Kermarrec
|
e72cd1468c
|
platforms/ac701: fix eth indent
|
2020-01-18 21:34:50 +01:00 |
|
Florent Kermarrec
|
eca9bf10ae
|
mimas_v7: cleanup, make it similar to others boards
|
2020-01-16 11:24:09 +01:00 |
|
Florent Kermarrec
|
54f39b600a
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mimas_a7: fix copyrights
|
2020-01-16 11:02:11 +01:00 |
Feliks
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206ec34551
|
platforms/mimas_a7: add support
|
2020-01-14 23:31:03 -05:00 |
|
Florent Kermarrec
|
50d550c911
|
kx2: cleanup, fix copyright
|
2020-01-13 17:22:33 +01:00 |
|
enjoy-digital
|
3811b58f32
|
Merge pull request #36 from Marrkson/master
ADD: KX2 and DDR3 support
|
2020-01-13 17:07:16 +01:00 |
|
Florent Kermarrec
|
c109b36fb9
|
travis: update/fix
|
2020-01-13 17:00:01 +01:00 |
Mark
|
13e5ca03a5
|
ADD: KX2 and DDR3 support
|
2020-01-13 14:21:54 +01:00 |
|
Florent Kermarrec
|
ab01f70e5c
|
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
|
2020-01-09 21:56:01 +01:00 |
Arnaud Durand
|
ab41cf5b79
|
Update ecp5_evn.py
|
2020-01-07 01:55:59 +01:00 |
|
Florent Kermarrec
|
c96e7c8fb9
|
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
|
2019-12-31 18:07:18 +01:00 |
|
Florent Kermarrec
|
2259042383
|
pipistrello: add copyrights
|
2019-12-31 17:44:24 +01:00 |
|
enjoy-digital
|
6324433e1c
|
Merge pull request #28 from zakgi/master
Adding initial support for Saanlima's Pipistrello LX45 board
|
2019-12-31 17:33:25 +01:00 |
msloniewski
|
9ed68d129f
|
platforms/de10lite: add additional configuration
Use single image with memory initialization
to make more space for SoC ROM sector.
|
2019-12-30 23:23:44 +01:00 |
|
msloniewski
|
28753a2c04
|
platforms/de10lite: remove UART pins from GPIO resource
V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
|
2019-12-30 23:06:58 +01:00 |
Giammarco Zacheo
|
39e428581f
|
Adding initial support for Saanlima's Pipistrello LX45 board
|
2019-12-29 18:29:11 -08:00 |
|
Florent Kermarrec
|
2a0fbcadd2
|
ac701: add pcie_x1 pins
|
2019-11-06 09:29:55 +01:00 |
|
Florent Kermarrec
|
b4eefa6c33
|
import: allow importing directly from litex_boards.platforms or litex_boards.targets
|
2019-09-03 15:30:20 +02:00 |
|
Florent Kermarrec
|
b84308cb58
|
list all platforms/targets in platforms.py, targets.py to ease import
|
2019-08-26 09:07:07 +02:00 |
|
DurandA
|
1abca7dcff
|
Turn litex_boards.community into module
|
2019-08-12 00:17:26 +02:00 |
|
enjoy-digital
|
ad21f15782
|
Merge pull request #10 from DurandA/ecp5-evn
Add ECP5 Evaluation Board
|
2019-08-09 12:37:36 +02:00 |
|
DurandA
|
9e6dccc277
|
Remove ECP5 Evaluation Board programmer
|
2019-08-09 11:54:49 +02:00 |
|
DurandA
|
4126ed21d5
|
Add X5 clock and PLL to ECP5 Evaluation Board
|
2019-08-09 11:54:38 +02:00 |
|
DurandA
|
c7444fe19c
|
Add ECP5 Evaluation Board
|
2019-08-09 09:45:13 +02:00 |
|
Florent Kermarrec
|
9f3ed82097
|
keep up to date with LiteX
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
|
2019-08-07 08:47:08 +02:00 |
|
Florent Kermarrec
|
a88970a67f
|
move trellis board from community to partner
|
2019-07-12 19:23:21 +02:00 |
David Shah
|
a07e88d761
|
community: Add TrellisBoard
Signed-off-by: David Shah <dave@ds0.me>
|
2019-07-09 15:52:28 +01:00 |
|
Florent Kermarrec
|
aeddb93729
|
add copyright header to all files, udpate.
|
2019-06-24 12:13:54 +02:00 |
|
Florent Kermarrec
|
44d01edab9
|
dispatch platforms/targets by level of support
|
2019-06-10 18:59:49 +02:00 |