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1824 Commits

Author SHA1 Message Date
Florent Kermarrec 867489d855 xilinx_zcu106: Add PCIe Gen3 X4 support. 2022-04-01 10:01:06 +02:00
enjoy-digital 6f8a745e4f
Merge pull request #380 from fjullien/ti60_add_mipi_rx 
efinix: ti60f225 add MIPI RX
 2022-03-29 15:51:22 +02:00
Franck Jullien 299d4d66d6 efinix: ti60f225 add MIPI RX 2022-03-29 15:29:59 +02:00
Florent Kermarrec e705e4e053 test/test_targets: Exclude efinix_t8f81_dev_kit. 2022-03-28 15:43:02 +02:00
enjoy-digital 13e5062793
Merge pull request #379 from chmousset/add_t8_devkit 
[enh] added efinix t8f81 dev kit
 2022-03-28 14:58:21 +02:00
enjoy-digital e6a9f44580
Merge pull request #378 from antmicro/add-missing-peripherals 
DDR4 datacenter: add missing peripherals
 2022-03-28 14:40:22 +02:00
enjoy-digital 83d7c3fb39
Merge pull request #377 from Johnsel/arduino_mkrvidor4000 
Board support for Arduino MKR Vidor 4000
 2022-03-28 14:34:59 +02:00
enjoy-digital 1541b77781
Merge pull request #376 from hansfbaier/master 
qmtech_5cefa2: make serial pins consistent with other boards
 2022-03-28 14:30:28 +02:00
Charles-Henri Mousset 7a68dcc79b [enh] added efinix t8f81 dev kit 2022-03-26 09:52:20 +01:00
Alessandro Comodi 33516a40f4 antmicro_datacenter: add missing peripherals 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-25 13:49:41 +01:00
Alessandro Comodi 77cb866233 antmicro_datacenter: add HDMI output 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-25 10:03:07 +01:00
John Simons 501c50ff79 Fixed serial port comments hinting the correct pins. 2022-03-24 08:04:47 -07:00
John Simons 901942bda6 Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================-- 
CPU:BUS:E 32-bit @ 4GiB
CSR:16-bit @ 48MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 21.3MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
 2022-03-24 07:39:14 -07:00
Hans Baier e445c9ec71 qmtech_5cefa2: make serial pins consistent with other boards 2022-03-24 18:52:28 +07:00
Florent Kermarrec c081177d77 pynq_z1/zybo_z7: Update .xci (With changes from #99). 2022-03-24 09:15:36 +01:00
enjoy-digital 010099b306
Merge pull request #375 from smunaut/adrv2crr 
ADRV2CRR: Fixing some of my screwups that I just noticed now
 2022-03-24 08:37:47 +01:00
Sylvain Munaut bcedf573e0 adi_adrv2crr: Add IO definition for the AD9545 reset line 
We use PULLUP on it so that the AD9545 is by default held out
of reset without the user having to do anything ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut cdb78efd3c adi_adrv2crr: Document I2C devices attached 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Sylvain Munaut 6c31f16df2 adi_adrv2crr: Fix I2C signal assignement 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-23 20:42:30 +01:00
Florent Kermarrec bb974ae1af decklink_quad_hdmi_recorder: Add pcie_lanes parameter and 4x/8x support. 2022-03-23 15:24:49 +01:00
Florent Kermarrec 73458ae9d7 decklink_quad_hdmi_recorder: Add Serial/UART pins. 2022-03-23 11:08:51 +01:00
enjoy-digital d399f33dda
Merge pull request #374 from smunaut/adrv2crr 
adi_adrv2crr: Upgrade part to speedgrade 2
 2022-03-23 09:09:57 +01:00
enjoy-digital 4ca527974b
Merge pull request #373 from goran-mahovlic/patch-1 
faster sdcard boot on 2.0
 2022-03-23 08:07:49 +01:00
Sylvain Munaut dc92584681 adi_adrv2crr: Upgrade part to speedgrade 2 
Even though the schematic and bom call for speedgrade 1, this was only for
the prototypes.

All productions units have been updated to speedgrade 2.

See this thread:
https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade

And the official HDL project for the board:
https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-22 23:36:41 +01:00
Florent Kermarrec ce4b627e3c targets: Remove l2_size workaround (no longer required). 2022-03-22 19:13:23 +01:00
Goran Mahovlic 68c23e9251
faster sdcard boot on 2.0 2022-03-22 17:54:12 +01:00
Florent Kermarrec 2a206def0f targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less). 2022-03-22 17:32:35 +01:00
Matt Johnston 53c221a1fa butterstick: set ethernet rx_delay to 0ns 
The Microchip KSZ9031RNX PHY on the Butterstick has a default 1.2ns
internal RX delay so we shouldn't add the default 2ns MAC delay.

In testing with Linux on vexriscv I haven't seen any difference either
way, but with liteeth in Microwatt I have seen 30%+ packet loss when
receiving from certain ethernet devices (RTL8153 and AX88179 usb-gige
adapters, a GS105 switch didn't show the problem). Setting RX delay=0
resolves the problem. A TX delay is still required by the PHY.
 2022-03-22 13:51:03 +08:00
John Simons b8b0aead28 Added basic support for Arduino MKR Vidor 4000 2022-03-21 18:54:29 -07:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec d90e260414 targets/digilent_atlys: Fix target. 2022-03-21 17:38:02 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec eb8657f515 gsd_orangecrab: Revert dm_remapping (Useful when built with VexRiscv-SMP and native LiteDRAM interface). 2022-03-18 12:56:13 +01:00
Florent Kermarrec 3ebad7f7cc gsd_orangecrab/butterstick: Add assert on devices. 2022-03-18 10:44:21 +01:00
Florent Kermarrec 9faa805ab9 alinx_ax7010: Review/Cleanup. 2022-03-17 11:31:02 +01:00
enjoy-digital 3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010 
Add ALINX AX7010 board support
 2022-03-17 09:52:04 +01:00
Florent Kermarrec 0f82db26da rcs_artic_term_bmc_card: Fix is -> ==. 2022-03-17 09:45:47 +01:00
Florent Kermarrec 496b2cfab9 targets/gowin: Switch to get_bitstream_filename. 2022-03-17 09:40:10 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Yonggang Liu 94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py 2022-03-17 11:24:24 +08:00
Yonggang Liu 0e7145b4a1
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py 2022-03-17 11:21:42 +08:00
Florent Kermarrec 0745162a29 xilinx_zcu102: Review/Cleanup for consistency with others boards. 
Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
 2022-03-16 18:47:05 +01:00
enjoy-digital 8003dcdd02
Merge pull request #370 from jwfaye/jwfaye-patch-1 
add xilinx_zcu102 platform
 2022-03-16 18:39:54 +01:00
Joseph Faye adbcc2e547
add zcu102 target file 2022-03-16 15:55:37 +01:00
Joseph Faye f4a48e51d7
add xilinx_zcu102 platform 2022-03-16 15:37:02 +01:00
Yonggang Liu 9dad1cb244
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py 2022-03-15 15:51:13 +08:00
Yonggang Liu 5365c7fce4
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py 2022-03-15 15:50:09 +08:00
enjoy-digital a962d8249f
Merge pull request #366 from gsomlo/gls-nexys-video-sata-pll 
targets/nexys-video: Add support for sata pll refclk
 2022-03-13 12:30:58 +01:00
enjoy-digital 0ada1e7d55
Merge pull request #365 from antmicro/lpddr4-pin-fix 
lpddr4_test_board: Fix button pin
 2022-03-13 12:29:37 +01:00
Yonggang Liu 9c55773275
Add files via upload 
Add zynq_xc7z010 board support
 2022-03-12 12:33:41 +08:00