Florent Kermarrec
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da61aabc5b
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targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
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2020-05-05 16:32:10 +02:00 |
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Florent Kermarrec
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2d9543b65e
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targets: add build/load parameters on all targets.
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2020-05-05 15:11:47 +02:00 |
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Florent Kermarrec
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4185a019f5
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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Florent Kermarrec
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5f629c203b
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targets/vcu118: fix clk500 typo.
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2020-04-07 13:53:22 +02:00 |
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Florent Kermarrec
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3b91e96c42
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targets/add_constant: avoid specifying value when value is None (=default)
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2020-03-26 09:47:22 +01:00 |
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Florent Kermarrec
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555bf6c4dc
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targets/Ultrascale(+): enable USDDRPHY_DEBUG.
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2020-03-26 09:17:09 +01:00 |
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Florent Kermarrec
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83e6fb29f8
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targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
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2020-03-21 12:43:39 +01:00 |
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Florent Kermarrec
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74a5ffb9ef
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targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
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2020-03-10 16:58:30 +01:00 |
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Florent Kermarrec
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e2a66090ee
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targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
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2020-03-10 16:55:22 +01:00 |
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Florent Kermarrec
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cf58550bba
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targets/Ultrascale+: use USPDDRPHY.
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2020-03-10 16:06:48 +01:00 |
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Florent Kermarrec
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f279fe9d33
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vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
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2020-02-25 10:35:18 +01:00 |
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Florent Kermarrec
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88a1f80db1
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vc707/vcu118: use proper copyrights
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2020-02-25 09:03:52 +01:00 |
Fei Gao
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373e74f435
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add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
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2020-02-24 14:20:47 -05:00 |