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1,637 Commits 9 Branches 14 Tags 11 MiB
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13 Commits

Author SHA1 Message Date
Florent Kermarrec 45494f60e0 targets: Change SoC/Software headers generation behaviour (Now only generated with --build). 
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
 2022-05-06 15:14:32 +02:00
Florent Kermarrec 4fbf2fc7de targets: Replace self.add_wb_master with self.bus.add_master. 2022-04-21 15:32:19 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible. 
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
 2022-04-21 12:19:45 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Florent Kermarrec fccb952c4b target: Remove ident_version=True no longer required. 2022-01-18 17:13:02 +01:00
Florent Kermarrec 53dc00eab7 targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description. 
Also do minor adjustments while doing this.
 2022-01-05 17:06:40 +01:00
Joey Bushagour 1920db3535 Add with_led_chaser argument to constructor of boards using LedChaser submodule. 2021-07-06 16:39:37 -05:00
Florent Kermarrec 47bdf5f759 targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required). 2021-03-25 10:11:24 +01:00
Florent Kermarrec d73bd2f7ce targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
Florent Kermarrec 1ac1c6857f targets/xilinx: add false path constraint between sys_clk and pll.clkin. 
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
 2021-01-07 00:02:46 +01:00
Gwenhael Goavec-Merou 8d1095224f add support for redpitaya14/16 2020-11-26 06:54:11 +01:00