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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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acorn_cle_215.py
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targets/acorn_cle_215: use new generate_litepcie_software functions and add --driver argument to generate driver.
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2020-06-03 08:20:43 +02:00 |
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aller.py
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targets/pcie: use generate_litepcie_software on all targets with PCIe.
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2020-06-03 08:30:54 +02:00 |
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alveo_u250.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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arty.py
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targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3).
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2020-06-25 11:21:24 +02:00 |
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arty_s7.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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c10lprefkit.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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camlink_4k.py
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targets: rename gateware-toolchain parameter to toolchain.
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2020-06-02 13:45:05 +02:00 |
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colorlight_5a_75x.py
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targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e).
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2020-06-10 23:14:37 +02:00 |
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de0nano.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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de1soc.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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de2_115.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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de10lite.py
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de10lite: simplify vga terminal.
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2020-06-11 19:59:32 +02:00 |
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de10nano.py
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de10nano/Mister: review/simplify.
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2020-06-11 19:54:55 +02:00 |
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ecp5_evn.py
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targets: rename gateware-toolchain parameter to toolchain.
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2020-06-02 13:45:05 +02:00 |
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ecpix5.py
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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2020-06-29 16:42:53 +02:00 |
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fomu.py
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targets: add build/load parameters on all targets.
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2020-05-05 15:11:47 +02:00 |
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forest_kitten_33.py
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forest_kitten_33: add minimal target and use es1.
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2020-05-25 12:26:52 +02:00 |
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genesys2.py
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targets: simplify Ethernet/Etherbone integration on targets with both.
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2020-05-29 19:20:27 +02:00 |
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hadbadge.py
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targets: rename gateware-toolchain parameter to toolchain.
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2020-06-02 13:45:05 +02:00 |
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icebreaker.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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kc705.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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kcu105.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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kx2.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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linsn_rv901t.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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logicbone.py
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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2020-06-29 16:42:53 +02:00 |
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mercury_xu5.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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mimas_a7.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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minispartan6.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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nereid.py
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targets/pcie: use generate_litepcie_software on all targets with PCIe.
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2020-06-03 08:30:54 +02:00 |
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netv2.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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nexys4ddr.py
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targets: add fixed sdcard clock on boards with SDCard support.
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2020-06-25 11:20:38 +02:00 |
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nexys_video.py
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targets: add fixed sdcard clock on boards with SDCard support.
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2020-06-25 11:20:38 +02:00 |
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orangecrab.py
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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2020-06-29 16:42:53 +02:00 |
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pano_logic_g2.py
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pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone.
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2020-05-29 10:41:35 +02:00 |
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pipistrello.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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simple.py
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targets: rename gateware-toolchain parameter to toolchain.
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2020-06-02 13:45:05 +02:00 |
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tagus.py
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targets/pcie: use generate_litepcie_software on all targets with PCIe.
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2020-06-03 08:30:54 +02:00 |
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trellisboard.py
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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2020-06-29 16:42:53 +02:00 |
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ulx3s.py
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targets: add fixed sdcard clock on boards with SDCard support.
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2020-06-25 11:20:38 +02:00 |
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vc707.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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vcu118.py
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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versa_ecp5.py
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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2020-06-29 16:42:53 +02:00 |
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zcu104.py
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Merge pull request #78 from antmicro/jboc/spd-read
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2020-05-27 14:56:31 +02:00 |
1356ebb416