Florent Kermarrec 2cef54a909 targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). ... This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.		2020-07-26 11:58:42 +02:00
..
platforms	arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.	2020-07-24 16:29:35 +02:00
prog	platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).	2020-06-23 11:55:50 +02:00
targets	targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).	2020-07-26 11:58:42 +02:00
tools	tools/extract_xdc_pins: +x.	2020-05-16 11:12:46 +02:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00