litex-boards/litex_boards/prog
Florent Kermarrec 0ce7f8354c Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  3 2022 18:59:46
 BIOS CRC passed (5f29afcc)

 LiteX git sha1: a4cc859d

--=============== SoC ==================--
CPU:		VexRiscv @ 80MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
2022-05-03 19:04:06 +02:00
..
openocd_butterstick.cfg
openocd_colorlight_5a_75b.cfg
openocd_ecpix5.cfg
openocd_evn_ecp5.cfg
openocd_fpc_iii.cfg
openocd_genesys2.cfg platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
openocd_limesdr_mini_v2.cfg
openocd_litex_acorn_baseboard.cfg
openocd_marblemini.cfg
openocd_max10_blaster.cfg
openocd_max10_blaster2.cfg
openocd_netv2_rpi.cfg
openocd_nexys_video.cfg
openocd_trellisboard.cfg
openocd_versa_ecp5.cfg platforms: make sure all traditional platforms have a create_programmer method. 2020-05-05 13:34:57 +02:00
openocd_xc6_ft232.cfg
openocd_xc6_ft2232.cfg prog/openocd: fix openocd_xc6 cfgs. 2020-05-27 08:48:16 +02:00
openocd_xc7_ft232.cfg
openocd_xc7_ft2232.cfg
openocd_xc7_ft4232.cfg