Jevin Sweval 9e5224ca49 Add JTAGbone support to Terasic DECA ... Along the way I added UARTbone support to DECA as well for debugging. Examples: ./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg litex_term crossover ./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag		2022-01-27 14:13:58 -08:00
..
openocd_butterstick.cfg	prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone).	2021-10-27 17:27:07 +02:00
openocd_colorlight_5a_75b.cfg	colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2).	2020-11-23 10:13:57 +01:00
openocd_ecpix5.cfg	Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration	2021-01-28 12:00:28 +01:00
openocd_evn_ecp5.cfg
openocd_fpc_iii.cfg	Add FPC-III board support.	2021-01-28 09:51:42 -07:00
openocd_genesys2.cfg	platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).	2020-06-23 11:55:50 +02:00
openocd_marblemini.cfg
openocd_max10_blaster.cfg	Add JTAGbone support to Terasic DECA	2022-01-27 14:13:58 -08:00
openocd_max10_blaster2.cfg	Add JTAGbone support to Terasic DECA	2022-01-27 14:13:58 -08:00
openocd_netv2_rpi.cfg
openocd_nexys_video.cfg
openocd_trellisboard.cfg
openocd_versa_ecp5.cfg
openocd_xc6_ft232.cfg
openocd_xc6_ft2232.cfg
openocd_xc7_ft232.cfg
openocd_xc7_ft2232.cfg
openocd_xc7_ft4232.cfg	Add target for LPDDR4 Test Board	2021-03-30 14:50:02 +02:00