Florent Kermarrec 621d45cd9e digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code. ... sys4x/sys4x_dqs/idelay clks can be disabled when integrated-main-ram is used.		2022-01-24 19:16:07 +01:00
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platforms	Add tweaks to Arty board to support yosys+nextpnr toolchain	2022-01-24 02:06:34 -03:00
prog	prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone).	2021-10-27 17:27:07 +02:00
targets	digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code.	2022-01-24 19:16:07 +01:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py	spartan_edge_accelerator: Add seeedstudio prefix and seeedsstudio to vendors list.	2022-01-06 09:06:27 +01:00