Sylvain Munaut b3caabcca3 di_adrv2crr_fmc: Bump PCIe to 8 lanes ... There used to be an issue with 8 lanes litepcie USP for that board when it was first added, but it's been solved now, so might as well use all the available lanes Signed-off-by: Sylvain Munaut <tnt@246tNt.com>		2024-02-05 11:43:02 +01:00
..
platforms	sipeed_tang_mega_138k: Added PCIe reset and other pins from sipeed documentation	2024-01-13 04:38:54 -03:00
prog	prog/openocd_ecpix5.cfg: refresh/fix	2023-12-13 18:34:02 +01:00
targets	di_adrv2crr_fmc: Bump PCIe to 8 lanes	2024-02-05 11:43:02 +01:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00