183 lines
8.2 KiB
Python
Executable File
183 lines
8.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import terasic_sockit
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoVGAPHY
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from litex.build.io import DDROutput
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from litedram.modules import AS4C32M16
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from litedram.phy import HalfRateGENSDRPHY, GENSDRPHY
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# DRAM Module for XS board v2.2 ----------------------------------------------------------------------
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# FIXME: Move to litedram.modules.
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from litedram.modules import _TechnologyTimings, _SpeedgradeTimings, SDRModule
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class W9825G6KH6(SDRModule):
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"""
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Winbond W9825G6KH-6 chip on Mister SDRAM XS board v2.2
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This is the smallest and cheapest module.
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running it at 100MHz (1:2 if system clock is 50MHz)
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works well on my SoCKit and all 32MB test error free
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I get a number of data errors if I run it at 50MHz,
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so this defaults to 1:2. If you want to use a higher
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system clock (eg 100MHz), you might want to consider
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using 1:1 clocking, because the -6 speedgrade
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can be clocked up to 166MHz (CL3) or 133MHz (CL2)
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"""
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# geometry
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nbanks = 4
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nrows = 8192
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ncols = 512
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@staticmethod
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def clock_cycles_to_ns(cycles, clk_freq, sdram_rate) -> float:
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d = {
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"1:1" : 1,
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"1:2" : 2,
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"1:4" : 4
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}
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return cycles / (d[sdram_rate] * clk_freq) / 1e-9
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def __init__(self, clk_freq, sdram_rate):
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# The datasheet specifies tWr in clock cycles, not in
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# ns but to me it looks like litedram expects
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# ns for these two parameters, so I have to convert them
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# to ns first.
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tWr = self.clock_cycles_to_ns(2, clk_freq, sdram_rate)
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tRRD = self.clock_cycles_to_ns(2, clk_freq, sdram_rate)
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self.technology_timings = _TechnologyTimings(tREFI=64e6/8000, tWTR=(2, None), tCCD=(1, None), tRRD=(None, tRRD))
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self.speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=tWr, tRFC=(None, 60), tFAW=None, tRAS=42)}
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super().__init__(clk_freq, sdram_rate)
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_video_terminal=False):
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self.sdram_rate = sdram_rate
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if with_video_terminal:
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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if with_sdram:
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if with_video_terminal:
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pll.create_clkout(self.cd_vga, 65e6)
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if with_sdram:
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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if with_sdram:
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None, with_video_terminal=False, **kwargs):
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platform = terasic_sockit.Platform(revision)
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# Defaults to UART over JTAG because serial is attached to the HPS and cannot be used.
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "jtag_atlantic"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on the Terasic SoCKit",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate, with_video_terminal=with_video_terminal)
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# SDR SDRAM --------------------------------------------------------------------------------
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if mister_sdram is not None:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}[mister_sdram]
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = sdrphy_mod(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Video Terminal ---------------------------------------------------------------------------
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if with_video_terminal:
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vga_pads = platform.request("vga")
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self.comb += [ vga_pads.sync_n.eq(0), vga_pads.blank_n.eq(1) ]
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self.specials += DDROutput(i1=1, i2=0, o=vga_pads.clk, clk=ClockSignal("vga"))
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self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga")
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self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on the Terasic SoCKit")
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parser.add_argument("--single-rate-sdram", action="store_true", help="clock SDRAM with 1x the sytem clock (instead of 2x)")
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parser.add_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card")
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parser.add_argument("--mister-sdram-xs-v24", action="store_true", help="Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--revision", default="revd", help="Board revision: revb (default), revc or revd")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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revision = args.revision,
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sdram_rate = "1:1" if args.single_rate_sdram else "1:2",
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mister_sdram = "xs_v22" if args.mister_sdram_xs_v22 else "xs_v24" if args.mister_sdram_xs_v24 else None,
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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