| .. |
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1bitsquared_icebreaker.py
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icebreaker/fomu: Update flashing and disconnect reset from SoC (will need proper support in iCE40PLL).
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2021-05-20 09:14:54 +02:00 |
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1bitsquared_icebreaker_bitsy.py
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targets: Add new 1bitsquared_icebreaker_bitsy target
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2021-06-21 22:11:53 +02:00 |
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__init__.py
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Move import Compat directly to litex_boards.__init__.py and simplify.
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2021-03-25 16:47:47 +01:00 |
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antmicro_lpddr4_test_board.py
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antmicro_lpddr4_test_board: fix ethernet rx delay issue
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2021-04-23 15:25:47 +02:00 |
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camlink_4k.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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colorlight_5a_75x.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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colorlight_i5.py
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targets: Minor cleanup, make sure all targets can be built with default settings.
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2021-03-29 16:22:39 +02:00 |
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decklink_intensity_pro_4k.py
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decklink_intensity_pro_4k: Add WIP.
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2021-06-30 09:06:00 +02:00 |
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decklink_mini_4k.py
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targets/decklink_mini_4k: Fix typos.
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2021-06-24 19:13:18 +02:00 |
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decklink_quad_hdmi_recorder.py
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decklink_quad_hdmi_recorder: Remove WIP (SoC + DDR3 now working) and add build/use instructions.
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2021-07-02 15:54:57 +02:00 |
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digilent_arty.py
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targets/digilent_arty: Add default value for CRG's with_mapped_flash.
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2021-07-02 09:33:06 +02:00 |
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digilent_arty_s7.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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digilent_basys3.py
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basys3: Review/Simplify and fix build.
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2021-05-25 08:44:26 +02:00 |
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digilent_genesys2.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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digilent_nexys4ddr.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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digilent_nexys_video.py
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targets/digilent_nexys_video: Add specific Video PLL to give more flexibility on supported Video Timings.
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2021-03-30 10:17:50 +02:00 |
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ego1.py
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Add E-Elements Ego1 initial board support.
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2021-04-12 08:20:46 +02:00 |
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enclustra_mercury_kx2.py
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enclustra_mercury_kx2: Comment user_led2/3 (Conflicting with DRAM pins).
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2021-06-16 11:54:52 +02:00 |
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enclustra_mercury_xu5.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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fpc_iii.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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gsd_orangecrab.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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hackaday_hadbadge.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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kosagi_fomu.py
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icebreaker/fomu: Update flashing and disconnect reset from SoC (will need proper support in iCE40PLL).
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2021-05-20 09:14:54 +02:00 |
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kosagi_netv2.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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lambdaconcept_ecpix5.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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lattice_crosslink_nx_evn.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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lattice_crosslink_nx_vip.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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lattice_ecp5_evn.py
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boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
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2021-03-25 14:11:17 +01:00 |
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lattice_ice40up5k_evn.py
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Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
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2021-05-04 12:19:21 +02:00 |
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lattice_versa_ecp5.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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linsn_rv901t.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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logicbone.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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mist.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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muselab_icesugar.py
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muselab_icesugar/trenz_cyc1000: +x.
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2021-05-25 08:46:33 +02:00 |
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numato_aller.py
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targets: Minor cleanup, make sure all targets can be built with default settings.
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2021-03-29 16:22:39 +02:00 |
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numato_mimas_a7.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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numato_nereid.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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numato_tagus.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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pano_logic_g2.py
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targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
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2021-03-25 10:11:24 +01:00 |
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qmtech_ep4ce15.py
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qmtech ep4ce15: Add daughterboard support, add spiflash
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2021-05-15 13:16:43 +07:00 |
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qmtech_wukong.py
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Qmtech Wukong: updates
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2021-04-10 16:26:25 +02:00 |
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qmtech_xc7a35t.py
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QMTech XC7A35T: fix argument parser description
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2021-05-08 08:49:07 +07:00 |
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radiona_ulx3s.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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redpitaya.py
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targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
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2021-03-25 10:11:24 +01:00 |
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saanlima_pipistrello.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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scarabhardware_minispartan6.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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siglent_sds1104xe.py
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targets: Update names in build descriptions.
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2021-04-29 11:56:52 +02:00 |
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simple.py
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targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
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2021-03-25 10:11:24 +01:00 |
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sqrl_acorn.py
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targets: Update names in build descriptions.
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2021-04-29 11:56:52 +02:00 |
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sqrl_fk33.py
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targets: Minor cleanup, make sure all targets can be built with default settings.
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2021-03-29 16:22:39 +02:00 |
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sqrl_xcu1525.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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terasic_de0nano.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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terasic_de1soc.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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terasic_de2_115.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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terasic_de10lite.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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terasic_de10nano.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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terasic_deca.py
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terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality).
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2021-03-27 08:58:49 +01:00 |
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terasic_sockit.py
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terasic_sockit: fix: make video clock also optional as video terminal is optional
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2021-04-27 08:52:11 +07:00 |
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tinyfpga_bx.py
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targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
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2021-03-25 10:11:24 +01:00 |
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trellisboard.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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trenz_c10lprefkit.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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trenz_cyc1000.py
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muselab_icesugar/trenz_cyc1000: +x.
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2021-05-25 08:46:33 +02:00 |
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trenz_max1000.py
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trenz_max1000: Review/Cleanup.
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2021-06-16 18:04:55 +02:00 |
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trenz_te0725.py
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Add Trenz te0725 initial board support.
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2021-04-12 08:16:45 +02:00 |
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trenz_tec0117.py
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trenz_tec0117: Use new DDROutput to generate SDRAM Clk.
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2021-07-14 10:02:58 +02:00 |
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xilinx_ac701.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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xilinx_alveo_u250.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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xilinx_alveo_u280.py
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fix cmdltncy, with_led
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2021-04-27 17:30:56 -04:00 |
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xilinx_kc705.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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xilinx_kcu105.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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xilinx_vc707.py
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targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
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2021-03-29 16:03:19 +02:00 |
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xilinx_vcu118.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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xilinx_zcu104.py
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targets/add_sdram: Simplify call by removing useless arguments.
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2021-03-29 15:28:31 +02:00 |
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xilinx_zybo_z7.py
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boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
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2021-03-25 14:11:17 +01:00 |
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ztex213.py
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targets: Minor cleanup, make sure all targets can be built with default settings.
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2021-03-29 16:22:39 +02:00 |
ba8321a3ab