Florent Kermarrec c1088befe5 targets/CRG: Add rst signal when missing. ... Allow properly reseting the PLL from the SoC.		2023-07-26 16:56:27 +02:00
..
platforms	platforms/ti60_f225: Add connector numbering to ease review/schematic comparison.	2023-07-21 09:08:22 +02:00
prog	Basic SoC for Opal Kelly XEM8320	2023-02-28 13:19:12 -07:00
targets	targets/CRG: Add rst signal when missing.	2023-07-26 16:56:27 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00