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litex-boards/litex_boards
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msloniewski cace17e162 targets/de10lite: refactor setting up clock domains 
Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
2019-12-30 23:25:43 +01:00
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community targets/de10lite: refactor setting up clock domains 2019-12-30 23:25:43 +01:00
official targets/versa_ecp5: fix compilation with diamond 2019-12-06 16:16:19 +01:00
partner Comment out template overrides for now. 2019-12-30 19:23:05 +01:00
__init__.py init repo with litex official boards 2019-06-10 17:11:36 +02:00
platforms.py platforms/target: only catch ModuleNotFoundError exceptions to improve error reporting (thanks mwelling) 2019-11-16 09:40:30 +01:00
targets.py platforms/target: only catch ModuleNotFoundError exceptions to improve error reporting (thanks mwelling) 2019-11-16 09:40:30 +01:00