msloniewski cace17e162 targets/de10lite: refactor setting up clock domains ... Use PLL to generate clock for both sys clock domain and clock domain for sdram. Additionally set up clock domain for VGA periph.		2019-12-30 23:25:43 +01:00
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platforms	platforms/de10lite: add additional configuration	2019-12-30 23:23:44 +01:00
targets	targets/de10lite: refactor setting up clock domains	2019-12-30 23:25:43 +01:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00